This document does not discuss the contents of the standard design example, but you can explore the design in SOPC Builder and refer to the readme.txt in the design directory to gain a better understanding.
System Requirements
To complete the steps in this document, you need the following:
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Quartus II software, version 7.2 or higher Nios II Embedded Development Suite 7.2 or higher Nios II Development Kit, Cyclone II, or Stratix II Edition
Design Files
The design files that accompany this application note are included in the examples directory installed with the Nios II Embedded Design Suite. The default location is: \\nios2eds\examples
Designing with SignalTap II and SOPC Builder Systems
The following steps guide you through opening a Quartus II project that includes an SOPC Builder-generated system module, and creating a SignalTap II ELA to analyze signals in the system.
Open and Generate the SOPC Builder System
1. Copy the entire folder for the Nios II standard example design for your particular board to a location where it can be edited. This folder is located in the following path:
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If you are using Verilog as your primary HDL: //nios2eds/examples/verilog//standard
2 Preliminary
Altera Corporation
Designing with SignalTap II and SOPC Builder Systems
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If you are using VHDL as your primary HDL: //nios2eds/examples/vhdl//standard
2. 3. 4.
Open the Quartus II software. On the File menu, click Open Project. Browse to the location where you copied the standard example design. Select the NiosII__standard.qpf file and click Open. On the Assignments menu, click Settings. In the Settings dialog box, under the Compilation Process Settings section, select Incremental Compilation. Set the Incremental Compilation option to Off as shown in Figure 2. By turning off the Incremental Compilation option, pre-synthesis signals can be added to the SignalTap II ELA in the later sections. Pre-synthesis signals exist after design elaboration, but before any synthesis optimizations are done. This set of signals should reflect your register transfer level (RTL) signals.

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