Section I. MAX II Device Family Data Sheet
This section provides designers with the data sheet specifications for MAX II devices. The chapters contain feature definitions of the internal architecture, Joint Test Action Group (JTAG) and in-system programmability (ISP) information, DC operating conditions, AC timing parameters, and ordering information for MAX II devices. This section includes the following chapters:
■ ■ ■ ■ ■ ■
Chapter 1, Introduction Chapter 2, MAX II Architecture Chapter 3, JTAG and In-System Programmability Chapter 4, Hot Socketing and Power-On Reset in MAX II Devices Chapter 5, DC and Switching Characteristics Chapter 6, Reference and Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook.
October 2008
Altera Corporation
MAX II Device Handbook
http://www.cpld.cn
提供CPLD芯片解密,CPLD破解服务
010-62245566
I–2
Section I: MAX II Device Family Data Sheet Revision History
MAX II Device Handbook
October 2008 Altera Corporation
http://www.cpld.cn
提供CPLD芯片解密,CPLD破解服务
010-62245566
1. Introduction
MII51001-1.8
Introduction
The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m, 6-layermetal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices offer high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP), MAX II devices are designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control, and device configuration control.

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