第 41 卷第 4 期 2010 年 8 月
中南大学学报(自然科学版) Journal of Central South University (Science and Technology)
Vol.41 No.4 Aug. 2010
一种基于电平位移电路的低电压全摆幅 CMOS 运放
潘学文,周继承,郑旭强 (中南大学 物理科学与技术学院,湖南 长沙,410083)
摘 要:为解决阈值电压对电源电压和输入信号的受限问题,提出一种实用的电平位移电路,为运放的输入级提
供良好的电平位移.采用互补金属氧化物半导体(CMOS) 0.5 m 工艺设计的低电压全摆幅 CMOS 运算放大器, 中间级采用适合低电压工作的低压宽摆幅共源共栅结构,输出级采用传统的 Class A 类得到轨至轨的输出.采用 Hspice 软件对所设计的电路进行仿真.研究结果表明:当电源电压降至或者小于 NMOS 与 PMOS 的阈值电压之 和时,在任何共模输入电压下,该运放都能正常工作,实现输入级的全摆幅和恒跨导;在 1.3 V 单电源供电情形 下直流开环增益达 106.5 dB,单位增益带宽为 2.3 MHz,功耗 178.8 W.电路结构简单紧凑,具有实用的电平位 移功能,适合于低电压应用. 关键词:CMOS 运放;全摆幅;仿真;电平位移技术 中图分类号:TN 402 文献标志码:A 文章编号:16727207(2010)04147305
A level-shifting circuit based on low-voltage rail-to-rail CMOS op-amp
PAN Xue-wen, ZHOU Ji-cheng, ZHENG Xu-qiang
(School of Physics Science and Technology, Central South University, Changsha 410083, China) Abstract: A level-shifting circuit was proposed to solve the supply voltage and input signal limited by threshold voltage, which offers a level-shifting voltage for input stage. A low-voltage rail-to-rail op-amp was designed by CMOS 0.5 m, the middle gain stage uses the low voltage, wide swing cascade structure which is suitable to work in low voltage, and the output stage uses the traditional class A to reach rail-to-rail. With a single 1.3 V supply voltage, the whole circuit was simulated in Hspice. The results show that when the supply voltage is equal to or lower than the sum of NMOS threshold voltage and PMOS threshold voltage, the op-amp can also work well in any common mode input voltage. It reaches rail-to-rail common mode input range and constant gm. The direct current gain is 106.5 dB while the unit gain bandwidth is 2.3 MHz, and 178.8 W power dissipation. For its simple and compact structure, this op-amp cell is suitable for low voltage application. Key words: CMOS op-amp; rail-to-rail; simulation; level-shifting technique
近年来,随着 CMOS 工艺的发展,器件特征尺寸 减小,集成电路的集成度提高, 使得集成电路向着低 为了适应低压低功耗的发展 压低功耗的方向发展[12]. 趋势,低电压,高功效,高性能的模拟电路单元的设 计成为人们关注的焦点

下一页