TB-FMCL-USB30 Startup Guide 1 Rev.1.00 TB-FMCL-USB30 Startup Guide Rev.1.00 TB-FMCL-USB30 Startup Guide 2 Rev.1.00 Revision History Version Date Description Publisher Rev.1.00 2012/06/25 Initial release Yoshioka Please read this software license agreement carefully before downloading or using the Software. By downloading the Software, you are agreeing to be bound by the terms of this software license. If you do not agree to the terms of this software license, you may not download, install or use the Software. Software License Agreement Tokyo Electron Device Limited ("Licensor") and Customer ("Licensee") agree to the terms of this software license as follows: 1. Licensor grants Licensee a nonexclusive license to use, copy, modify and distribute the Software solely for development, production and sell of Licensee's own products. 2. Licensee acknowledges that all title to the copyright and all other intellectual property rights in and to the Software, its accompanying documentation and any copy made by Licensee are the exclusive property of and remain with Licensor. 3. The Software is provided AS IS and without any warranty of any kind. In no event will Licensor be liable to Licensee for any software problems (no obligation to render technical support), infringement of any intellectual property rights, or any direct, indirect, consequential, incidental damages or loss of profit arising out of the use of this Software by Licensee or other third parties. 4. (1)Licensee shall not disclose any confidential information relating to Licensor's technical and marketing information on the Software (hereafter referred to as "Confidential Information"). Licensee shall not disclose the Confidential Information even within its organization except for authorized employees and the board members. (2)The Confidential Information does not include information which (a) is within the public domain, (b) is already known to Licensee before the time it receives the same from Licensor or disclosed by a third party as a matter of right and (c) is independently developed by Licensee. TB-FMCL-USB30 Startup Guide 3 Rev.1.00 Table of Contents 1. Overview.6 2. Design Development.6 2.1. Board 6 2.2. Development Environment 6 2.3. Reference Document.6 3. Distributed Data.7 3.1. Distributed Data Structure 7 4. Board Setup.8 4.1. Carrier Board Jumper Settings.8 4.2. TB-FMCL-USB30 Jumper Settings 9 4.3. Board and Cable Connections.9 5. FPGA Configuration.10 5.1. Configuration Step 1.10 5.2. Configuration Step 2.11 5.3. Configuration Step 3.11 5.4. Configuration Step 4.12 5.5. Configuration Step 5.12 5.6. Configuration Step 6.13 5.7. Configuration Step 7.13 5.8. Configuration Step 8.14 6. Installing Driver Software.15 6.1. Open Device Manager.15 6.2. Searching for Driver Software 15 6.3. Specifying a Driver Store Folder.16 6.4. Executing Driver Installation.16 6.5. Completion of Driver Software Installation 17 7. Downloading USB3.0 Firmware.17 7.1. Running CyControl.exe 17 7.2. Programming the Firmware.18 7.3. Completion of Programming.18 8. Running Sample Application 19 8.1. Run FMCFx3RefDesign.exe.19 8.2. Single Access Test (Internal)19 8.3. Single Access Test (AXI)20 8.4. Burst Access Test 20 8.5. Speed Test.21 9. EDK Design Overview.22 9.1. System Block Diagram 22 9.2. Description of Each Block (Data Sheet or User Guide #: Functional Description)22 10. Running EDK Base System Builder 23 10.1. Starting Base System Builder.23 10.2. Base System Builder – Board Selection.24 10.3. Base System Builder – Peripheral Selection.24 TB-FMCL-USB30 Startup Guide 4 Rev.1.00 11. Embedment of FX3 to AXI Bridge.25 11.1. Copy to pcores 25 11.2. Rescan User Repositories.25 11.3. Add IP.26 11.4. Add IP Instance to Design 26 11.5. IP Config Dialog.27 11.6. New IP Connections 27 11.7. Bus Connect 1 28 11.8. Bus Connect 2 28 11.9. clock_generator Config 1.29 11.10. clock_generator Config 2.29 11.11. clock_generator Config 3.30 11.12. Clock_generator Config 4.30 11.13. "Net" Column 31 11.14. Adding clock_generator Port 31 11.15. Configuring FX3 to AXI Bridge Port.32 11.16. Editing UCF 33 11.17. Adding TB-FMCL-USB30 Related Restrictions to UCF 33 11.18. Creating Config Data 34 11.19. FPGA Configuration.34 11.20. Board Testing.34 12. FAQ 35 12.1. Will the board run on XXX's PC?35 12.2. What firmware/application development environment is required?35 12.3. Which carrier board is recommended?35 12.4. Does the TB-FMCL-USB30 board run in standalone?35 12.5. Is an USB3.0 cable attached?35 12.6. How fast transfer rate is?35 12.7. Not recognized as USB when connected to PC. What are the causes of this?35 12.8. Can the board function as a USB3.0 Host Controller?36 12.9. Is the associated software source code provided?36 12.10. Can other vendor's carrier boards be connected?36 12.11. Tell us the operating system (OS) support for sample software?36 12.12. Can the board run on Windows 7 64bit?36 12.13. Are samples corresponding to USB2.0 OTG available?36 List of Figures Figure 3-1 Distributed Data Structure.7 Figure 4-1 Carrier Board Jumper Settings 8 Figure 4-2 TB-FMCL-USB30 Jumper Settings.9 Figure 4-3 TB-FMCL-USB30 Cable Connections 9 Figure 5-1 Boundary Scan 10 Figure 5-2 Initialize Chain 11 Figure 5-3 Assign Configuration Files 11 Figure 5-4 Select Configuration File.12 Figure 5-5 Attach SPI or BPI PROM 12 TB-FMCL-USB30 Startup Guide 5 Rev.1.00 Figure 5-6 Device Programing Properties.13 Figure 5-7 Program 13 Figure 5-8 Successful.14 Figure 6-1 Updating Driver Software.15 Figure 6-2 Specifying a Search Method.15 Figure 6-3 Specifying a Driver Store Folder 16 Figure 6-4 Install Driver without Signature.16 Figure 6-5 Completion of Driver Software Installation 17 Figure 7-1 CyControl.17 Figure 7-2 Specifying Firmware 18 Figure 7-3 Completion of Programming.18 Figure 8-1Sample Application Structure.19 Figure 8-2Single Access Test (Internal)19 Figure 8-3 Single Access Test (AXI)20 Figure 8-4 Burst Access Test.20 Figure 8-5 Speed Test 21 Figure 9-1 Block Diagram 22 Figure 10-1 Starting Base System Builder 23 Figure 10-2 Board Selection 24 Figure 10-3 Peripheral Selection.24 Figure 11-1 Rescan User Repositories 25 Figure 11-2 Add IP.26 Figure 11-3 Add IP Instance to Design.26 Figure 11-4 IP Config Dialog 27 Figure 11-5 Connect IP 27 Figure 11-6 Bus Connect 1.28 Figure 11-7 Bus Connect 2.28 Figure 11-8 clock_generator Config 1 29 Figure 11-9 clock_generator Config 2 29 Figure 11-10 clock_generator Config 3.30 Figure 11-11 clock_generator Config 4 30 Figure 11-12 "Net" Column.31 Figure 11-13 Adding clock_generator Port.31 Figure 11-14 Configuring FX3 to AXI Bridge Port 32 Figure 11-15 Editing UCF.33 Figure 11-16 Editing UCF.33 Figure 11-17 Creating Config Data.34 TB-FMCL-USB30 Startup Guide 6 Rev.1.00 1. Overview This document provides a description about how to unpack and use the TB-FMCL-USB30 board in the early part and how to embed interface circuits in the carrier board FPGA design in the latter part. For frequently asked questions, refer to Section 12.FAQ. Read them before buying. 2. Design Development This document assumes the following design environment. 2.1. Board TB-6S-LX150T-IMG2 (hereafter referred to as "carrier board") TB-FMCL-USB30 2.2. Development Environment Xilinx EDK 14.1 (Microsoft Windows 7 Professional 32bit) Xilinx Platform Studio (XPS) 2.3. Reference Document TED - TB-6S-LX150T-IMG2_HWUserManual_x.xx.pdf TED - TB-6S-LX150T-IMG2_EDK-AXI_BSB_x.xx.pdf TED - TB-FMCL-USB30_HWUserManual_x.xx.pdf TED - TB-6S-LX150T-IMG2_USB30_ReferenceDesign_x.xx.pdf (Please download the latest version of documents from support website) TB-FMCL-USB30 Startup Guide 7 Rev.1.00 3. Distributed Data This section describes distributed data used in this document. 3.1. Distributed Data Structure Zip files available from the TED Support Website When the TB-FMCL-USB30_Startup_1_00.zip is expanded, the following data files will appear (partly omitted) Figure 3-1 Distributed Data Structure Create a "C:/work" folder and store "ready_for_download", "pcores" and "ucf" in it. Folder Structure: C:/work/ready_for_download C:/work/pcores C:/work/ucf TB-FMCL-USB30 Startup Guide 8 Rev.1.00 4. Board Setup This section provides a brief description of board settings for operational testing. 4.1. Carrier Board Jumper Settings Figure 4-1 shows the carrier board jumper settings. Figure 4-1 Carrier Board Jumper Settings TB-FMCL-USB30 Startup Guide 9 Rev.1.00 4.2. TB-FMCL-USB30 Jumper Settings Figure 4-2 shows the TB-FMCL-USB30 jumper settings. Figure 4-2 TB-FMCL-USB30 Jumper Settings 4.3. Board and Cable Connections Connect TB-FMCL-USB30 to the carrier board connector CN3 LPC1, Xilinx Platform Cable II to the power supply, and PC to TB-FMCL-USB30 using a USB3.0 cable (TypeA to TypeB). JTAG Power USB3.0?TypeB Figure 4-3 TB-FMCL-USB30 Cable Connections TB-FMCL-USB30 Startup Guide 10 Rev.1.00 5. FPGA Configuration This section describes how to configure the FPGA on the carrier board. Make sure that the board has been set up as shown in Section 4 Board Setup and then turn on the power switch of the carrier board. The following steps are simple instructions for operating iMPACT that is attached to the Xilinx ISE Design Suite. 5.1. Configuration Step 1 Figure 5-1 Boundary Scan TB-FMCL-USB30 Startup Guide 11 Rev.1.00 5.2. Configuration Step 2 Figure 5-2 Initialize Chain 5.3. Configuration Step 3 Figure 5-3 Assign Configuration Files TB-FMCL-USB30 Startup Guide 12 Rev.1.00 5.4. Configuration Step 4 Figure 5-4 Select Configuration File Config data folder: C:/work/ready_for_download/FPGA/S6/GPIF_II_AUX_BRAM_TOP.bit 5.5. Configuration Step 5 Figure 5-5 Attach SPI or BPI PROM TB-FMCL-USB30 Startup Guide 13 Rev.1.00 5.6. Configuration Step 6 Figure 5-6 Device Programing Properties 5.7. Configuration Step 7 Figure 5-7 Program TB-FMCL-USB30 Startup Guide 14 Rev.1.00 5.8. Configuration Step 8 Figure 5-8 Successful TB-FMCL-USB30 Startup Guide 15 Rev.1.00 6. Installing Driver Software This section describes how to install driver software on the computer connecting to the board. 6.1. Open Device Manager Open Device Manager by selecting Windows Control Panel -> Device Manager. A device icon with mark "!" will appear (e.g. "WestBridge"). Click on this device and then Update Driver Software. Figure 6-1 Updating Driver Software 6.2. Searching for Driver Software Select Browse my computer for driver software to search for driver software you want. Figure 6-2 Specifying a Search Method TB-FMCL-USB30 Startup Guide 16 Rev.1.00 6.3. Specifying a Driver Store Folder Select Search for driver software in this location to specify a driver store folder you want. Figure 6-3 Specifying a Driver Store Folder Driver Store Folder: C:/work/ready_for_download/Sys/win7/x86 6.4. Executing Driver Installation A Windows security warning will appear. Click Install this driver software anyway. Figure 6-4 Install Driver without Signature TB-FMCL-USB30 Startup Guide 17 Rev.1.00 6.5. Completion of Driver Software Installation When the software installation has been completed successfully, click on the Close button. Figure 6-5 Completion of Driver Software Installation 7. Downloading USB3.0 Firmware This section provides information on how to download USB3.0 Firmware. 7.1. Running CyControl.exe Run C:/work/ready_for_download/CyControl.exe to download the firmware. Figure 7-1 CyControl TB-FMCL-USB30 Startup Guide 18 Rev.1.00 7.2. Programming the Firmware From the CyControl menu, select Program => FX3 => RAM and specify C:/work/ready_for_download/Firm/FMCFX3RDesign.img in the Select file to download dialog. Open -Click- Select -Click- Figure 7-2 Specifying Firmware 7.3. Completion of Programming When programming is successfully completed, TB-FMCL-FX3 Reference Design USB3.0 will appear in the CyControl menu. Figure 7-3 Completion of Programming TB-FMCL-USB30 Startup Guide 19 Rev.1.00 8. Running Sample Application This section describes how to run sample application and perform operational testing of the sample design. 8.1. Run FMCFx3RefDesign.exe Run C:/work/ready_for_download/App/FMCFx3RefDesign.exe. The FMCFx3RefDesign.exe sample application has functions as shown in Figure 8-1. Figure 8-1Sample Application Structure 8.2. Single Access Test (Internal) First, read internal registers in the FX3 to AXI Bridge circuit. Check the Internal Reg radio button and click Read. If values other than "00000000" can be read, it means the circuit operates properly. Figure 8-2Single Access Test (Internal) TB-FMCL-USB30 Startup Guide 20 Rev.1.00 8.3. Single Access Test (AXI) Then, write and read the AXI BRAM that is connected to the FX3 to AXI Bridge circuit. Following Data 0x, type a 32-bit value (a5a5a5a5) for Write -> Read operations. If this test is completed successfully, the written value can be read properly. Figure 8-3 Single Access Test (AXI) 8.4. Burst Access Test Perform data read and write operations to AXI BRAM for each file. Set Write File and Read File as follows and perform the operations in order of Write => Read => Verify. Write File C:/work/ready_for_download/App/testdata/inc_64k.bin Read File C:/work/ready_for_download/App/testdata/read00.bin Figure 8-4 Burst Access Test If the operations are completed successfully, [OK:]Verify successfully will appear in the status bar. TB-FMCL-USB30 Startup Guide 21 Rev.1.00 8.5. Speed Test USB transfer rate between PC and board can be measured. Set Direction and Size and click on the Start button. Data transfer speed will be displayed. Its value varies greatly dependent on PC configuration. Figure 8-5 Speed Test TB-FMCL-USB30 Startup Guide 22 Rev.1.00 9. EDK Design Overview This section describes how to create an EDK design using FX3 to AXI Bridge for EDK that is contained in C:/work/pcores. A brief EDK design overview is provided below. 9.1. System Block Diagram Figure 9-1 shows the design block diagram. MicroBlaze contained in the diagram is not used in this document. M icroB laze A X IInterconnect (C rossbarC onfiguration) A X IInterconnect (S hared-B usC onfiguration) AX IG P IO AX IG P IO LE D(8bit) D IP -S W(10bit) AX IS 6M em ory C ontroller DD R 2S D R A M B lockR A M (8KB yte) LM BB R A M C ontroller LM BB R A M C ontroller P rocS ysR eset C lockG enerator 1 0 0 M H z 6 0 0 M H z 6 0 0 M H z 1 8 0 d e g 20 0 M H z P /N 1 0 0 M H z 1 0 0 M H z 6 0 0 M H z 6 0 0 M H z 1 8 0 d e g M ic ro B la z eR e s e t D e b ug R e s e t In te rc o n n e c tR e s e t S ys te m R e s e t L o ck e d R e s e t (P S W 5 ) L o c k e d 1 0 0 M H z In tr 5 0 M H z 5 0 M H z 1 8 0 d e g 5 0 M H z 2 7 0 d e g FX 3toA X IB ridge U S B 3.0FX 3D evice 5 0 M H z 5 0 M H z 1 8 0 d e g 5 0 M H z 2 7 0 d e g Figure 9-1 Block Diagram 9.2. Description of Each Block (Data Sheet or User Guide #: Functional Description) MicroBlaze: UG081: Soft CPU core LMB BRAM Controller: DS452: BRAM memory controller for LMB connection Block RAM: DS444: Xilinx primitive Block RAM AXI Interconnect: DS768: AXI interconnect, two modes AXI S6 Memory Controller: UG416: Spartan-6 MCB memory controller AXI GPIO DS744: GPIO for LED and DIP-SW connection Proc Sys Reset: DS406: Various reset generation and management Clock Generator: DS614: Various clock generation and management FX3 to AXI Bridge: Downloaded from TED Support Web TB-FMCL-USB30 Startup Guide 23 Rev.1.00 10. Running EDK Base System Builder This section describes how to create a base design of the carrier board by EDK. The design project will be created in the following folder. Project Folder C:/work/xps_usb30 The following subsections provide operational procedures of Xilinx ISE Design Suite – Xilinx Platform Studio. 10.1. Starting Base System Builder 1.?Project?Location -C:\work\xps_usb30\system.xmp- 2.?OK -Click- Figure 10-1 Starting Base System Builder TB-FMCL-USB30 Startup Guide 24 Rev.1.00 10.2. Base System Builder – Board Selection Figure 10-2 Board Selection 10.3. Base System Builder – Peripheral Selection Figure 10-3 Peripheral Selection TB-FMCL-USB30 Startup Guide 25 Rev.1.00 11. Embedment of FX3 to AXI Bridge This section describes how to embed FX3 to AXI Bridge in the EDK base design. 11.1. Copy to pcores Write a whole folder containing C:/work/pcores on C:/work/xps_usb30/pcores. This will result in: C:/work/xps_usb30/pcores/fx3_to_axi_bridge_s6_v1_00_a C:/work/xps_usb30/pcores/fx3_to_axi_bridge_k7_v1_00_a 11.2. Rescan User Repositories Figure 11-1 Rescan User Repositories TB-FMCL-USB30 Startup Guide 26 Rev.1.00 11.3. Add IP FX3?AXI?Bridge?S6 -Double?Click- Figure 11-2 Add IP 11.4. Add IP Instance to Design Figure 11-3 Add IP Instance to Design TB-FMCL-USB30 Startup Guide 27 Rev.1.00 11.5. IP Config Dialog Figure 11-4 IP Config Dialog 11.6. New IP Connections Figure 11-5 Connect IP TB-FMCL-USB30 Startup Guide 28 Rev.1.00 11.7. Bus Connect 1 1.?axi4_0 -Select- 2.?axi_0:microblaz... -Click- Figure 11-6 Bus Connect 1 11.8. Bus Connect 2 Figure 11-7 Bus Connect 2 TB-FMCL-USB30 Startup Guide 29 Rev.1.00 11.9. clock_generator Config 1 Figure 11-8 clock_generator Config 1 11.10. clock_generator Config 2 Figure 11-9 clock_generator Config 2 TB-FMCL-USB30 Startup Guide 30 Rev.1.00 11.11. clock_generator Config 3 Figure 11-10 clock_generator Config 3 11.12. Clock_generator Config 4 Figure 11-11 clock_generator Config 4 TB-FMCL-USB30 Startup Guide 31 Rev.1.00 11.13. "Net" Column Figure 11-12 "Net" Column 11.14. Adding clock_generator Port Create new Net(s) for "clock_generator_0" CLKOUT3 ~ 5. The following Net names are assigned by setting each Net to "New Connection". CLKOUT3 clock_generator_0_CLKOUT3 CLKOUT4 clock_generator_0_CLKOUT4 CLKOUT5 clock_generator_0_CLKOUT5 Figure 11-13 Adding clock_generator Port TB-FMCL-USB30 Startup Guide 32 Rev.1.00 11.15. Configuring FX3 to AXI Bridge Port Set up signal connection for each "fx3_to_axi_bridge_s6_0" port. Each Net is configured as follows: GPIF_CLK clock_generator_0_CLKOUT3 GPIF_CLK_180 clock_generator_0_CLKOUT4 GPIF_CLK_270 clock_generator_0_CLKOUT5 AXI_CLK clk_100_0000MHzPLL0 (IO_IF)fx3_gpif2_0Make Ports External 1.?fx3_axi_bridge_s6_0?[? ] -Click- 2.?clock_generator_0_CLKOUT3/4/5 -Select- 3.?clk_100_0000MHzPLL0 -Select- 4.?Make?External -Select- Figure 11-14 Configuring FX3 to AXI Bridge Port TB-FMCL-USB30 Startup Guide 33 Rev.1.00 11.16. Editing UCF 1.?Project -Click- 2.?UCF?File -Double?Click- Figure 11-15 Editing UCF 11.17. Adding TB-FMCL-USB30 Related Restrictions to UCF Copy and paste the contents of the following file to the lines following the last line of the UCF that has been opened in the previous section and overwrite the UCF by selecting File -> Save in the menu. C:/work/ucf/TB-6S-LX150T-IMG2_FMC1.txt Figure 11-16 Editing UCF TB-FMCL-USB30 Startup Guide 34 Rev.1.00 11.18. Creating Config Data Generate?Bitstream -Click- Figure 11-17 Creating Config Data 11.19. FPGA Configuration Configure the following configuration data based on the procedure described in Section 5. FPGA Configuration. C:/work/xps_usb30/implementation/system.bit 11.20. Board Testing Test the circuit on the board based on the procedure described in Section 8.Running Sample Application. If the test is successful, user can perform a write/read operation to the DDR3 SDRAM on the carrier board. TB-FMCL-USB30 Startup Guide 35 Rev.1.00 12. FAQ This section provides information about Frequently Asked Questions regarding TB-FMCL-USB30. 12.1. Will the board run on XXX's PC? USB logo program is not available. So, connection to all PCs cannot be guaranteed. For connectivity information, please refer to the TED Support Web. TB-FMCL-USB30_Checked_PC_information_x.xx.pdf The list is updated as needed. We welcome your feedback. 12.2. What firmware/application development environment is required? Our sample application & firmware is developed under the following environment. Application: Microsoft Visual C++ 2008 Professional Firmware: Cypress EZ-USB FX3 SDK ver.1.01 12.3. Which carrier board is recommended? The following boards provide reference design, which is available on the TED Support Website. TB-6S-LX150T-IMG2 TB-7K-325K-IMG 12.4. Does the TB-FMCL-USB30 board run in standalone? The board needs the power supply from the carrier board. So, it cannot be used in standalone. 12.5. Is an USB3.0 cable attached? The cable is not attached to the board. User must buy it at electronics retail store. As for maximum cable length, up to 1.5m cable connection has been demonstrated in our labo. 12.6. How fast transfer rate is? Our labo test using our sample application demonstrated approximately 200MByte/sec transfer rate. The transfer rate has a correlation to PC specs and USB3.0 Host Controller performance. Cypress's driver and SDK may improve the performance. 12.7. Not recognized as USB when connected to PC. What are the causes of this? Compared to the commercial USB3.0 devices, in some cases the board may not be recognized as USB, for example : (1) The driver version of USB3.0 Host Controller is too old or certain specific versions are not supported. (2) Cable length from USB3.0 Host controller device on PC to USB3.0 port is too long. These situations may be improved by connecting a USB3.0 HUB. Reference: Buffalo Kokuyo Supply's BSH4A04U3 Series TB-FMCL-USB30 Startup Guide 36 Rev.1.00 12.8. Can the board function as a USB3.0 Host Controller? No, it cannot function as an USB3.0 Host Controller. 12.9. Is the associated software source code provided? Free sample software and applications can be downloaded from TED Support Web. The drivers use a Cypress binary distribution. 12.10. Can other vendor's carrier boards be connected? We have not tested these connections. It would be possible if the following conditions are met (in this case changes to the reference design are required). (1) FMC LPC connectors (IO 2pin) are installed (2) 2.5V IO voltage for FMC is supported 12.11. Tell us the operating system (OS) support for sample software? The following operating system support has been demonstrated in our labo. Windows 7 32bit Windows 7 64bit Windows XP 32bit 12.12. Can the board run on Windows 7 64bit? Yes, it can. However, since driver signing (KMCS) is not provided, it is needed to disable driver signing feature. Reference URL: http://windows.microsoft.com/ja-jp/windows-vista/Advanced-startup-options-including-safe-mode 12.13. Are samples corresponding to USB2.0 OTG available? No, samples corresponding to USB2.0 OTG are not available. TB-FMCL-USB30 Startup Guide 37 Rev.1.00 PLD Solution Dept. PLD Division URL: http://solutions.inrevium.com/ E-mail: psd-support@teldevice.co.jp HEAD Quarter: Yokohama East Square, 1-4 Kinko-cho, Kanagawa-ku, Yokohama City, Kanagawa, Japan 221-0056 TEL: +81-45-443-4016 FAX: +81-45-443-4058
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TB-FMCL-USB30 Startup Guide 1 Rev.1.00 TB-FMCL-USB30 Startup Guide Rev.1.00 TB-FMCL-USB30 Startup Guide 2 Rev.1.00 Revision History Version Date Description Publisher Rev.1.00 2012/06/25 Initial release Yoshioka Please read this software license agreement carefully before downloading or using the Software. By downloading the Software, you are agreeing to be bound by the terms of this software license. If you do not agree to the terms of this software license, you may not download, install or use the Software. Software License Agreement Tokyo Electron Device Limited ("Licensor") and Customer ("Licensee") agree to the terms of this software license as follows: 1. Licensor grants Licensee a nonexclusive license to use, copy, modify and distribute the Software solely for development, production and sell of Licensee's own products. 2. Licensee acknowledges that all title to the copyright and all other intellectual property rights in and to the Software, its accompanying documentation and any copy made by Licensee are the exclusive property of and remain with Licensor. 3. The Software is provided AS IS and without any warranty of any kind. In no event will Licensor be liable to Licensee for any software problems (no obligation to render technical support), infringement of any intellectual property rights, or any direct, indirect, consequential, incidental damages or loss of profit arising out of the use of this Software by Licensee or other third parties. 4. (1)Licensee shall not disclose any confidential information relating to Licensor's technical and marketing information on the Software (hereafter referred to as "Confidential Information"). Licensee shall not disclose the Confidential Information even within its organization except for authorized employees and the board members. (2)The Confidential Information does not include information which (a) is within the public domain, (b) is already known to Licensee before the time it receives the same from Licensor or disclosed by a third party as a matter of right and (c) is independently developed by Licensee. TB-FMCL-USB30 Startup Guide 3 Rev.1.00 Table of Contents 1. Overview.6 2. Design Development.6 2.1. Board 6 2.2. Development Environment 6 2.3. Reference Document.6 3. Distributed Data.7 3.1. Distributed Data Structure 7 4. Board Setup.8 4.1. Carrier Board Jumper Settings.8 4.2. TB-FMCL-USB30 Jumper Settings 9 4.3. Board and Cable Connections.9 5. FPGA Configuration.10 5.1. Configuration Step 1.10 5.2. Configuration Step 2.11 5.3. Configuration Step 3.11 5.4. Configuration Step 4.12 5.5. Configuration Step 5.12 5.6. Configuration Step 6.13 5.7. Configuration Step 7.13 5.8. Configuration Step 8.14 6. Installing Driver Software.15 6.1. Open Device Manager.15 6.2. Searching for Driver Software 15 6.3. Specifying a Driver Store Folder.16 6.4. Executing Driver Installation.16 6.5. Completion of Driver Software Installation 17 7. Downloading USB3.0 Firmware.17 7.1. Running CyControl.exe 17 7.2. Programming the Firmware.18 7.3. Completion of Programming.18 8. Running Sample Application 19 8.1. Run FMCFx3RefDesign.exe.19 8.2. Single Access Test (Internal)19 8.3. Single Access Test (AXI)20 8.4. Burst Access Test 20 8.5. Speed Test.21 9. EDK Design Overview.22 9.1. System Block Diagram 22 9.2. Description of Each Block (Data Sheet or User Guide #: Functional Description)22 10. Running EDK Base System Builder 23 10.1. Starting Base System Builder.23 10.2. Base System Builder – Board Selection.24 10.3. Base System Builder – Peripheral Selection.24 TB-FMCL-USB30 Startup Guide 4 Rev.1.00 11. Embedment of FX3 to AXI Bridge.25 11.1. Copy to pcores 25 11.2. Rescan User Repositories.25 11.3. Add IP.26 11.4. Add IP Instance to Design 26 11.5. IP Config Dialog.27 11.6. New IP Connections 27 11.7. Bus Connect 1 28 11.8. Bus Connect 2 28 11.9. clock_generator Config 1.29 11.10. clock_generator Config 2.29 11.11. clock_generator Config 3.30 11.12. Clock_generator Config 4.30 11.13. "Net" Column 31 11.14. Adding clock_generator Port 31 11.15. Configuring FX3 to AXI Bridge Port.32 11.16. Editing UCF 33 11.17. Adding TB-FMCL-USB30 Related Restrictions to UCF 33 11.18. Creating Config Data 34 11.19. FPGA Configuration.34 11.20. Board Testing.34 12. FAQ 35 12.1. Will the board run on XXX's PC?35 12.2. What firmware/application development environment is required?35 12.3. Which carrier board is recommended?35 12.4. Does the TB-FMCL-USB30 board run in standalone?35 12.5. Is an USB3.0 cable attached?35 12.6. How fast transfer rate is?35 12.7. Not recognized as USB when connected to PC. What are the causes of this?35 12.8. Can the board function as a USB3.0 Host Controller?36 12.9. Is the associated software source code provided?36 12.10. Can other vendor's carrier boards be connected?36 12.11. Tell us the operating system (OS) support for sample software?36 12.12. Can the board run on Windows 7 64bit?36 12.13. Are samples corresponding to USB2.0 OTG available?36 List of Figures Figure 3-1 Distributed Data Structure.7 Figure 4-1 Carrier Board Jumper Settings 8 Figure 4-2 TB-FMCL-USB30 Jumper Settings.9 Figure 4-3 TB-FMCL-USB30 Cable Connections 9 Figure 5-1 Boundary Scan 10 Figure 5-2 Initialize Chain 11 Figure 5-3 Assign Configuration Files 11 Figure 5-4 Select Configuration File.12 Figure 5-5 Attach SPI or BPI PROM 12 TB-FMCL-USB30 Startup Guide 5 Rev.1.00 Figure 5-6 Device Programing Properties.13 Figure 5-7 Program 13 Figure 5-8 Successful.14 Figure 6-1 Updating Driver Software.15 Figure 6-2 Specifying a Search Method.15 Figure 6-3 Specifying a Driver Store Folder 16 Figure 6-4 Install Driver without Signature.16 Figure 6-5 Completion of Driver Software Installation 17 Figure 7-1 CyControl.17 Figure 7-2 Specifying Firmware 18 Figure 7-3 Completion of Programming.18 Figure 8-1Sample Application Structure.19 Figure 8-2Single Access Test (Internal)19 Figure 8-3 Single Access Test (AXI)20 Figure 8-4 Burst Access Test.20 Figure 8-5 Speed Test 21 Figure 9-1 Block Diagram 22 Figure 10-1 Starting Base System Builder 23 Figure 10-2 Board Selection 24 Figure 10-3 Peripheral Selection.24 Figure 11-1 Rescan User Repositories 25 Figure 11-2 Add IP.26 Figure 11-3 Add IP Instance to Design.26 Figure 11-4 IP Config Dialog 27 Figure 11-5 Connect IP 27 Figure 11-6 Bus Connect 1.28 Figure 11-7 Bus Connect 2.28 Figure 11-8 clock_generator Config 1 29 Figure 11-9 clock_generator Config 2 29 Figure 11-10 clock_generator Config 3.30 Figure 11-11 clock_generator Config 4 30 Figure 11-12 "Net" Column.31 Figure 11-13 Adding clock_generator Port.31 Figure 11-14 Configuring FX3 to AXI Bridge Port 32 Figure 11-15 Editing UCF.33 Figure 11-16 Editing UCF.33 Figure 11-17 Creating Config Data.34 TB-FMCL-USB30 Startup Guide 6 Rev.1.00 1. Overview This document provides a description about how to unpack and use the TB-FMCL-USB30 board in the early part and how to embed interface circuits in the carrier board FPGA design in the latter part. For frequently asked questions, refer to Section 12.FAQ. Read them before buying. 2. Design Development This document assumes the following design environment. 2.1. Board TB-6S-LX150T-IMG2 (hereafter referred to as "carrier board") TB-FMCL-USB30 2.2. Development Environment Xilinx EDK 14.1 (Microsoft Windows 7 Professional 32bit) Xilinx Platform Studio (XPS) 2.3. Reference Document TED - TB-6S-LX150T-IMG2_HWUserManual_x.xx.pdf TED - TB-6S-LX150T-IMG2_EDK-AXI_BSB_x.xx.pdf TED - TB-FMCL-USB30_HWUserManual_x.xx.pdf TED - TB-6S-LX150T-IMG2_USB30_ReferenceDesign_x.xx.pdf (Please download the latest version of documents from support website) TB-FMCL-USB30 Startup Guide 7 Rev.1.00 3. Distributed Data This section describes distributed data used in this document. 3.1. Distributed Data Structure Zip files available from the TED Support Website When the TB-FMCL-USB30_Startup_1_00.zip is expanded, the following data files will appear (partly omitted) Figure 3-1 Distributed Data Structure Create a "C:/work" folder and store "ready_for_download", "pcores" and "ucf" in it. Folder Structure: C:/work/ready_for_download C:/work/pcores C:/work/ucf TB-FMCL-USB30 Startup Guide 8 Rev.1.00 4. Board Setup This section provides a brief description of board settings for operational testing. 4.1. Carrier Board Jumper Settings Figure 4-1 shows the carrier board jumper settings. Figure 4-1 Carrier Board Jumper Settings TB-FMCL-USB30 Startup Guide 9 Rev.1.00 4.2. TB-FMCL-USB30 Jumper Settings Figure 4-2 shows the TB-FMCL-USB30 jumper settings. Figure 4-2 TB-FMCL-USB30 Jumper Settings 4.3. Board and Cable Connections Connect TB-FMCL-USB30 to the carrier board connector CN3 LPC1, Xilinx Platform Cable II to the power supply, and PC to TB-FMCL-USB30 using a USB3.0 cable (TypeA to TypeB). JTAG Power USB3.0?TypeB Figure 4-3 TB-FMCL-USB30 Cable Connections TB-FMCL-USB30 Startup Guide 10 Rev.1.00 5. FPGA Configuration This section describes how to configure the FPGA on the carrier board. Make sure that the board has been set up as shown in Section 4 Board Setup and then turn on the power switch of the carrier board. The following steps are simple instructions for operating iMPACT that is attached to the Xilinx ISE Design Suite. 5.1. Configuration Step 1 Figure 5-1 Boundary Scan TB-FMCL-USB30 Startup Guide 11 Rev.1.00 5.2. Configuration Step 2 Figure 5-2 Initialize Chain 5.3. Configuration Step 3 Figure 5-3 Assign Configuration Files TB-FMCL-USB30 Startup Guide 12 Rev.1.00 5.4. Configuration Step 4 Figure 5-4 Select Configuration File Config data folder: C:/work/ready_for_download/FPGA/S6/GPIF_II_AUX_BRAM_TOP.bit 5.5. Configuration Step 5 Figure 5-5 Attach SPI or BPI PROM TB-FMCL-USB30 Startup Guide 13 Rev.1.00 5.6. Configuration Step 6 Figure 5-6 Device Programing Properties 5.7. Configuration Step 7 Figure 5-7 Program TB-FMCL-USB30 Startup Guide 14 Rev.1.00 5.8. Configuration Step 8 Figure 5-8 Successful TB-FMCL-USB30 Startup Guide 15 Rev.1.00 6. Installing Driver Software This section describes how to install driver software on the computer connecting to the board. 6.1. Open Device Manager Open Device Manager by selecting Windows Control Panel -> Device Manager. A device icon with mark "!" will appear (e.g. "WestBridge"). Click on this device and then Update Driver Software. Figure 6-1 Updating Driver Software 6.2. Searching for Driver Software Select Browse my computer for driver software to search for driver software you want. Figure 6-2 Specifying a Search Method TB-FMCL-USB30 Startup Guide 16 Rev.1.00 6.3. Specifying a Driver Store Folder Select Search for driver software in this location to specify a driver store folder you want. Figure 6-3 Specifying a Driver Store Folder Driver Store Folder: C:/work/ready_for_download/Sys/win7/x86 6.4. Executing Driver Installation A Windows security warning will appear. Click Install this driver software anyway. Figure 6-4 Install Driver without Signature TB-FMCL-USB30 Startup Guide 17 Rev.1.00 6.5. Completion of Driver Software Installation When the software installation has been completed successfully, click on the Close button. Figure 6-5 Completion of Driver Software Installation 7. Downloading USB3.0 Firmware This section provides information on how to download USB3.0 Firmware. 7.1. Running CyControl.exe Run C:/work/ready_for_download/CyControl.exe to download the firmware. Figure 7-1 CyControl TB-FMCL-USB30 Startup Guide 18 Rev.1.00 7.2. Programming the Firmware From the CyControl menu, select Program => FX3 => RAM and specify C:/work/ready_for_download/Firm/FMCFX3RDesign.img in the Select file to download dialog. Open -Click- Select -Click- Figure 7-2 Specifying Firmware 7.3. Completion of Programming When programming is successfully completed, TB-FMCL-FX3 Reference Design USB3.0 will appear in the CyControl menu. Figure 7-3 Completion of Programming TB-FMCL-USB30 Startup Guide 19 Rev.1.00 8. Running Sample Application This section describes how to run sample application and perform operational testing of the sample design. 8.1. Run FMCFx3RefDesign.exe Run C:/work/ready_for_download/App/FMCFx3RefDesign.exe. The FMCFx3RefDesign.exe sample application has functions as shown in Figure 8-1. Figure 8-1Sample Application Structure 8.2. Single Access Test (Internal) First, read internal registers in the FX3 to AXI Bridge circuit. Check the Internal Reg radio button and click Read. If values other than "00000000" can be read, it means the circuit operates properly. Figure 8-2Single Access Test (Internal) TB-FMCL-USB30 Startup Guide 20 Rev.1.00 8.3. Single Access Test (AXI) Then, write and read the AXI BRAM that is connected to the FX3 to AXI Bridge circuit. Following Data 0x, type a 32-bit value (a5a5a5a5) for Write -> Read operations. If this test is completed successfully, the written value can be read properly. Figure 8-3 Single Access Test (AXI) 8.4. Burst Access Test Perform data read and write operations to AXI BRAM for each file. Set Write File and Read File as follows and perform the operations in order of Write => Read => Verify. Write File C:/work/ready_for_download/App/testdata/inc_64k.bin Read File C:/work/ready_for_download/App/testdata/read00.bin Figure 8-4 Burst Access Test If the operations are completed successfully, [OK:]Verify successfully will appear in the status bar. TB-FMCL-USB30 Startup Guide 21 Rev.1.00 8.5. Speed Test USB transfer rate between PC and board can be measured. Set Direction and Size and click on the Start button. Data transfer speed will be displayed. Its value varies greatly dependent on PC configuration. Figure 8-5 Speed Test TB-FMCL-USB30 Startup Guide 22 Rev.1.00 9. EDK Design Overview This section describes how to create an EDK design using FX3 to AXI Bridge for EDK that is contained in C:/work/pcores. A brief EDK design overview is provided below. 9.1. System Block Diagram Figure 9-1 shows the design block diagram. MicroBlaze contained in the diagram is not used in this document. M icroB laze A X IInterconnect (C rossbarC onfiguration) A X IInterconnect (S hared-B usC onfiguration) AX IG P IO AX IG P IO LE D(8bit) D IP -S W(10bit) AX IS 6M em ory C ontroller DD R 2S D R A M B lockR A M (8KB yte) LM BB R A M C ontroller LM BB R A M C ontroller P rocS ysR eset C lockG enerator 1 0 0 M H z 6 0 0 M H z 6 0 0 M H z 1 8 0 d e g 20 0 M H z P /N 1 0 0 M H z 1 0 0 M H z 6 0 0 M H z 6 0 0 M H z 1 8 0 d e g M ic ro B la z eR e s e t D e b ug R e s e t In te rc o n n e c tR e s e t S ys te m R e s e t L o ck e d R e s e t (P S W 5 ) L o c k e d 1 0 0 M H z In tr 5 0 M H z 5 0 M H z 1 8 0 d e g 5 0 M H z 2 7 0 d e g FX 3toA X IB ridge U S B 3.0FX 3D evice 5 0 M H z 5 0 M H z 1 8 0 d e g 5 0 M H z 2 7 0 d e g Figure 9-1 Block Diagram 9.2. Description of Each Block (Data Sheet or User Guide #: Functional Description) MicroBlaze: UG081: Soft CPU core LMB BRAM Controller: DS452: BRAM memory controller for LMB connection Block RAM: DS444: Xilinx primitive Block RAM AXI Interconnect: DS768: AXI interconnect, two modes AXI S6 Memory Controller: UG416: Spartan-6 MCB memory controller AXI GPIO DS744: GPIO for LED and DIP-SW connection Proc Sys Reset: DS406: Various reset generation and management Clock Generator: DS614: Various clock generation and management FX3 to AXI Bridge: Downloaded from TED Support Web TB-FMCL-USB30 Startup Guide 23 Rev.1.00 10. Running EDK Base System Builder This section describes how to create a base design of the carrier board by EDK. The design project will be created in the following folder. Project Folder C:/work/xps_usb30 The following subsections provide operational procedures of Xilinx ISE Design Suite – Xilinx Platform Studio. 10.1. Starting Base System Builder 1.?Project?Location -C:\work\xps_usb30\system.xmp- 2.?OK -Click- Figure 10-1 Starting Base System Builder TB-FMCL-USB30 Startup Guide 24 Rev.1.00 10.2. Base System Builder – Board Selection Figure 10-2 Board Selection 10.3. Base System Builder – Peripheral Selection Figure 10-3 Peripheral Selection TB-FMCL-USB30 Startup Guide 25 Rev.1.00 11. Embedment of FX3 to AXI Bridge This section describes how to embed FX3 to AXI Bridge in the EDK base design. 11.1. Copy to pcores Write a whole folder containing C:/work/pcores on C:/work/xps_usb30/pcores. This will result in: C:/work/xps_usb30/pcores/fx3_to_axi_bridge_s6_v1_00_a C:/work/xps_usb30/pcores/fx3_to_axi_bridge_k7_v1_00_a 11.2. Rescan User Repositories Figure 11-1 Rescan User Repositories TB-FMCL-USB30 Startup Guide 26 Rev.1.00 11.3. Add IP FX3?AXI?Bridge?S6 -Double?Click- Figure 11-2 Add IP 11.4. Add IP Instance to Design Figure 11-3 Add IP Instance to Design TB-FMCL-USB30 Startup Guide 27 Rev.1.00 11.5. IP Config Dialog Figure 11-4 IP Config Dialog 11.6. New IP Connections Figure 11-5 Connect IP TB-FMCL-USB30 Startup Guide 28 Rev.1.00 11.7. Bus Connect 1 1.?axi4_0 -Select- 2.?axi_0:microblaz... -Click- Figure 11-6 Bus Connect 1 11.8. Bus Connect 2 Figure 11-7 Bus Connect 2 TB-FMCL-USB30 Startup Guide 29 Rev.1.00 11.9. clock_generator Config 1 Figure 11-8 clock_generator Config 1 11.10. clock_generator Config 2 Figure 11-9 clock_generator Config 2 TB-FMCL-USB30 Startup Guide 30 Rev.1.00 11.11. clock_generator Config 3 Figure 11-10 clock_generator Config 3 11.12. Clock_generator Config 4 Figure 11-11 clock_generator Config 4 TB-FMCL-USB30 Startup Guide 31 Rev.1.00 11.13. "Net" Column Figure 11-12 "Net" Column 11.14. Adding clock_generator Port Create new Net(s) for "clock_generator_0" CLKOUT3 ~ 5. The following Net names are assigned by setting each Net to "New Connection". CLKOUT3 clock_generator_0_CLKOUT3 CLKOUT4 clock_generator_0_CLKOUT4 CLKOUT5 clock_generator_0_CLKOUT5 Figure 11-13 Adding clock_generator Port TB-FMCL-USB30 Startup Guide 32 Rev.1.00 11.15. Configuring FX3 to AXI Bridge Port Set up signal connection for each "fx3_to_axi_bridge_s6_0" port. Each Net is configured as follows: GPIF_CLK clock_generator_0_CLKOUT3 GPIF_CLK_180 clock_generator_0_CLKOUT4 GPIF_CLK_270 clock_generator_0_CLKOUT5 AXI_CLK clk_100_0000MHzPLL0 (IO_IF)fx3_gpif2_0Make Ports External 1.?fx3_axi_bridge_s6_0?[? ] -Click- 2.?clock_generator_0_CLKOUT3/4/5 -Select- 3.?clk_100_0000MHzPLL0 -Select- 4.?Make?External -Select- Figure 11-14 Configuring FX3 to AXI Bridge Port TB-FMCL-USB30 Startup Guide 33 Rev.1.00 11.16. Editing UCF 1.?Project -Click- 2.?UCF?File -Double?Click- Figure 11-15 Editing UCF 11.17. Adding TB-FMCL-USB30 Related Restrictions to UCF Copy and paste the contents of the following file to the lines following the last line of the UCF that has been opened in the previous section and overwrite the UCF by selecting File -> Save in the menu. C:/work/ucf/TB-6S-LX150T-IMG2_FMC1.txt Figure 11-16 Editing UCF TB-FMCL-USB30 Startup Guide 34 Rev.1.00 11.18. Creating Config Data Generate?Bitstream -Click- Figure 11-17 Creating Config Data 11.19. FPGA Configuration Configure the following configuration data based on the procedure described in Section 5. FPGA Configuration. C:/work/xps_usb30/implementation/system.bit 11.20. Board Testing Test the circuit on the board based on the procedure described in Section 8.Running Sample Application. If the test is successful, user can perform a write/read operation to the DDR3 SDRAM on the carrier board. TB-FMCL-USB30 Startup Guide 35 Rev.1.00 12. FAQ This section provides information about Frequently Asked Questions regarding TB-FMCL-USB30. 12.1. Will the board run on XXX's PC? USB logo program is not available. So, connection to all PCs cannot be guaranteed. For connectivity information, please refer to the TED Support Web. TB-FMCL-USB30_Checked_PC_information_x.xx.pdf The list is updated as needed. We welcome your feedback. 12.2. What firmware/application development environment is required? Our sample application & firmware is developed under the following environment. Application: Microsoft Visual C++ 2008 Professional Firmware: Cypress EZ-USB FX3 SDK ver.1.01 12.3. Which carrier board is recommended? The following boards provide reference design, which is available on the TED Support Website. TB-6S-LX150T-IMG2 TB-7K-325K-IMG 12.4. Does the TB-FMCL-USB30 board run in standalone? The board needs the power supply from the carrier board. So, it cannot be used in standalone. 12.5. Is an USB3.0 cable attached? The cable is not attached to the board. User must buy it at electronics retail store. As for maximum cable length, up to 1.5m cable connection has been demonstrated in our labo. 12.6. How fast transfer rate is? Our labo test using our sample application demonstrated approximately 200MByte/sec transfer rate. The transfer rate has a correlation to PC specs and USB3.0 Host Controller performance. Cypress's driver and SDK may improve the performance. 12.7. Not recognized as USB when connected to PC. What are the causes of this? Compared to the commercial USB3.0 devices, in some cases the board may not be recognized as USB, for example : (1) The driver version of USB3.0 Host Controller is too old or certain specific versions are not supported. (2) Cable length from USB3.0 Host controller device on PC to USB3.0 port is too long. These situations may be improved by connecting a USB3.0 HUB. Reference: Buffalo Kokuyo Supply's BSH4A04U3 Series TB-FMCL-USB30 Startup Guide 36 Rev.1.00 12.8. Can the board function as a USB3.0 Host Controller? No, it cannot function as an USB3.0 Host Controller. 12.9. Is the associated software source code provided? Free sample software and applications can be downloaded from TED Support Web. The drivers use a Cypress binary distribution. 12.10. Can other vendor's carrier boards be connected? We have not tested these connections. It would be possible if the following conditions are met (in this case changes to the reference design are required). (1) FMC LPC connectors (IO 2pin) are installed (2) 2.5V IO voltage for FMC is supported 12.11. Tell us the operating system (OS) support for sample software? The following operating system support has been demonstrated in our labo. Windows 7 32bit Windows 7 64bit Windows XP 32bit 12.12. Can the board run on Windows 7 64bit? Yes, it can. However, since driver signing (KMCS) is not provided, it is needed to disable driver signing feature. Reference URL: http://windows.microsoft.com/ja-jp/windows-vista/Advanced-startup-options-including-safe-mode 12.13. Are samples corresponding to USB2.0 OTG available? No, samples corresponding to USB2.0 OTG are not available. TB-FMCL-USB30 Startup Guide 37 Rev.1.00 PLD Solution Dept. PLD Division URL: http://solutions.inrevium.com/ E-mail: psd-support@teldevice.co.jp HEAD Quarter: Yokohama East Square, 1-4 Kinko-cho, Kanagawa-ku, Yokohama City, Kanagawa, Japan 221-0056 TEL: +81-45-443-4016 FAX: +81-45-443-4058