Reliability and Failure Analysis of Electronic Components
By
Dr. Charles Surya, ENC
CD 636, ×6220
ensurya@polyu.edu.hk
For VLSI Circuits to be a useful and growing technology, 2 conditions must be satisfied:
Can be produced in large quantities at low cost
Cats can perform their functions throughout their intended lifetime
To lower the cost of manufacturing, one must determine the optimal size of the IC.
The optimal size is a compromise between several competing considerations:
Partitioning of the system
yield of good circuits
packaging and system assembly cost
reliability of complete system
Large number of IC's results in high yield and assembly cost
To arrive at an optimal division of the system, we must be able to predict the total system reliability as a function of the number of IC's of varying size
Mechanism of Yield Loss in VLSI
Cause for low yield falls into 3 basic categories:
Parametric processing problems
CKT design problems
random point defects in circuits
Processing Effects
Often a wafer is divided into regions good chips and bad chips (Fig. 1 p. 614, Sze)
This is most likely due to processing effects such as
Variations in thickness of oxide or polysilicon layers
Variations in resistance of implanted layers
Variations in width of lithographically defined features
Alignment of photomasks
e.g. PolySi gate lengths are shorter in thinner polySi regions than in thicker polySi regions. This may cause channel lengths to be too short and transistors cannot be turned off. This leads to excessive leakage current
Variations in thickness of deposited dielectric lead to variations in contact window size. This may lead to non-operative circuits if the circuits depend on having a low value of contact resistance.
Variations in the doping of implanted layers which also leads to variations in contact resistance

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