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  • DSP/ARM/CPLD/FPGA/MCU

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    Notes:
    ■Cin: 2.2μF or 4.7μF low ESR Capacitor Cout: 10μF low ESR Capacitor C1: 22pF Capacitor ■L:2.2μH,3.3μH or 4.7μH low DCR, high Frequency Power Inductor ■.R1+R2≈1M
    LAYOUT GUIDE
    2009.4
    WuXi Delicacy Science and Technology Co.,Ltd
    4/7
    DST6156
    DETAILED DESCRIPTION
    Current PWM Mode The DST6156 uses fast current loop and slow voltage loop to regulate the voltage with 50mA to 800mA loads. Slope compensated current mode PWM control provides stable switching and cycle-by-cycle current limit for excellent load and line responses and protection of the main switch(P-channel MOSFET) and synchronous rectifier(N-channel MOSFET). At the beginning of each clock cycle initiated by the clock signal (S), the P-channel MOSFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit is exceeded. After a certain time, called TDEAD, the N-channel rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel switch. Pulse-Skipping Mode At very light loads, the DST6156 automatically enters pulse-skipping mode(PSM).In PSM, the inductor current may reach zero or reverse, then the N-channel rectifier will be turned off and lots of schematic will go to sleep, with the cap powering the loads. Low-Dropout Mode The DST6156 offers a low input to output voltage difference, while still maintaining operation with the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation, depending on the load current and output voltage, can be calculated as
    VIN ( MIN ) VOUT ( MAX ) IOUT ( MAX ) ( RDS (ON ) P ( MAX ) RDC ( L ))

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