K
康芯科技
康芯科技 END IF; X END PROCESS; PROCESS( MMD ) BEGIN IF MMD = "00" THEN GRBP <= GRBX; -- 选择横彩条 ELSIF MMD = "01" THEN GRBP <= GRBY; -- 选择竖彩条 ELSIF MMD = "10" THEN GRBP <= GRBX XOR GRBY; --产生棋盘格 ELSE GRBP <= "000"; END IF; END PROCESS; PROCESS( CLK ) BEGIN IF CLK'EVENT AND CLK = '1' THEN -- 12MHz 13分频 IF FS = 12 THEN FS <= "0000"; ELSE FS <= (FS + 1); END IF; END IF; END PROCESS; FCLK <= FS(3); CCLK <= CC(4); PROCESS( FCLK ) BEGIN IF FCLK'EVENT AND FCLK = '1' THEN IF CC = 29 THEN CC <= "00000"; ELSE CC <= CC + 1; END IF; END IF; END PROCESS; PROCESS( CCLK ) BEGIN IF CCLK'EVENT AND CCLK = '0' THEN IF LL = 481 THEN LL <= "000000000"; ELSE LL 23 THEN HS1 <= '0'; --行同步 ELSE HS1 479 THEN VS1 <= '0'; --场同步 ELSE VS1 <= '1'; END IF; END PROCESS; PROCESS(CC, LL) BEGIN IF CC < 3 THEN GRBX <= "111"; -- 横彩条 ELSIF CC < 6 THEN GRBX <= "110"; ELSIF CC < 9 THEN GRBX <= "101"; ELSIF CC < 12 THEN GRBX <= "100"; ELSIF CC < 15 THEN GRBX <= "011"; ELSIF CC < 18 THEN GRBX <= "010"; ELSIF CC < 21 THEN GRBX <= "001"; ELSE GRBX <= "000"; END IF; IF LL < 60 THEN GRBY <= "111"; -- 竖彩条 ELSIF LL < 120 THEN GRBY <= "110"; ELSIF LL < 180 THEN GRBY <= "101"; ELSIF LL < 240 THEN GRBY <= "100"; ELSIF LL < 300 THEN GRBY <= "011"; ELSIF LL < 360 THEN GRBY <= "010"; ELSIF LL < 420 THEN GRBY <= "001"; ELSE GRBY <= "000"; END IF; END PROCESS; HS <= HS1 ; VS <= VS1 ;R <= GRB(2) ;G <= GRB(3) ; B <= GRB(1); END behav;
K
KX康芯科技
12.4 VGA图象显示控制器设计
VGAROMC VGA
R,G,B HS,VS
VGA时序控制
DATA8
EEPROM 或 FlashROM
ROM读取控制 模式控制 时钟 二分频
ADDR OE,CE MODF
CLK 50MHz时钟
图12-14 VGA图像控制器框图
【例12-8】 LIBRARY ieee; --图象显示顶层程序 USE ieee.std_logic_1164.all; ENTITY img IS port ( clk50MHz : IN STD_LOGIC; hs, vs, r, g, b : OUT STD_LOGIC ); END img; ARCHITECTURE modelstru OF img IS component vga640480 --VGA显示控制模块 PORT(clk : IN STD_LOGIC; rgbin : IN STD_LOGIC_VECTOR(2 downto 0); hs, vs, r, g, b : OUT STD_LOGIC; hcntout, vcntout : OUT STD_LOGIC_VECTOR(9 downto 0) end component; component imgrom --图象数据ROM,数据线3位;地址线12位 PORT(inclock : IN STD_LOGIC; address : IN STD_LOGIC_VECTOR(11 downto 0); q : OUT STD_LOGIC_VECTOR(2 downto 0) ); end component; signal rgb : STD_LOGIC_VECTOR(2 downto 0); signal clk25MHz : std_logic; signal romaddr : STD_LOGIC_VECTOR(11 downto 0); signal hpos, vpos : std_logic_vector(9 downto 0); BEGIN romaddr <= vpos(5 downto 0) & hpos(5 downto 0); process(clk50MHz) begin if clk50MHz'event and clk50MHz = '1' then clk25MHz clk25MHz, rgbin => rgb, hs => hs, vs => vs, r => r, g => g, b => b, hcntout => hpos, vcntout => vpos); i_rom : imgrom PORT MAP(inclock => clk25MHz, address => romaddr, q => rgb); END;

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