KX康芯科技
);
【例12-9】 X LIBRARY IEEE use IEEE.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vga640480 is port ( clk : in STD_LOGIC; hs, vs, r,g,b : out STD_LOGIC; rgbin : in std_logic_vector(2 downto 0); hcntout,vcntout : out std_logic_vector(9 downto 0)); end vga640480; architecture ONE of vga640480 is signal hcnt, vcnt : std_logic_vector(9 downto 0); begin hcntout <= hcnt; vcntout <= vcnt; process(clk) begin if (rising_edge(clk)) then if(hcnt < 800) then hcnt <= hcnt + 1; else hcnt '0'); end if; end if; end process; process(clk) begin if (rising_edge(clk)) then 接下页 if (hcnt = 640+8 ) then if(vcnt < 525) then vcnt <= vcnt + 1; else vcnt '0'); end if;
K
康芯科技
KX康芯科技
end if; end if; end process; process(clk) begin if (rising_edge(clk)) then if((hcnt>=640+8+8) and (hcnt<640+8+8+96 )) then hs<='0'; else hs = 480+8+2) and (vcnt<480+8+2+2)) then vs <= '0'; else vs<='1'; end if; end process; process(clk) begin if (rising_edge(clk)) then if (hcnt<640 and vcnt<480) then r<=rgbin(2); g<=rgbin(1); b<=rgbin(0); else r<='0'; g<='0'; b<='0'; end if; end if; end process; end ONE;
KX康芯科技
12.5 采用高速A/D的存储示波器设计
FPGA 模拟信号输入 地址发生计数器 时钟CLK DAC 高速ADC A/D采样控制器 分频器 锯齿波 双口RAM DAC 波形数据输出 Y 示波器 X
图12-15 存储示波器结构简图
KX康芯科技
12.5 采用高速A/D的存储示波器设计
图12-16
TLC5510引脚图
KX康芯科技
12.5 采用高速A/D的存储示波器设计
图12-17 TLC5510采样时序图
KX康芯科技
12.5 采用高速A/D的存储示波器设计
St 0
ADck<='1'; lock<='1'; dclk<='0';
图12-18
St 1
ADck<='0'; lock<='0'; dclk ADck<='1'; lock<='1'; dclk<='0';next_ads_state ADck<='0'; lock<='0'; dclk<='1';next_ads_state ADck<='0'; lock<='0'; dclk<='1';next_ads_state <= sta0; END CASE ; END PROCESS; 接下页
康芯科技
PROCESS (CLK,rst) KX BEGIN IF RST ='0' THEN ads_state <= sta0; ELSIF ( CLK'EVENT AND CLK='1') THEN ads_state <= next_ads_state; -- 在时钟上升沿,转换至下一状态 END IF; END PROCESS; PROCESS (lock,rst) -- 此进程中,在lock的上升沿,将转换好的数据锁入 BEGIN IF RST ='0' THEN data '0'); ELSIF lock'EVENT AND lock='1' THEN data <= D ; END IF; END PROCESS ; ADoe <= '0'; end ADCTRL;

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