Features
The MAX II CPLD has the following features:
■ ■ ■ ■ ■ ■ ■
Low-cost, low-power CPLD Instant-on, non-volatile architecture Standby current as low as 29 A Provides fast propagation delay and clock-to-output times Provides four global clocks with two clocks available per logic array block (LAB) UFM block up to 8 Kbits for non-volatile storage MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels Bus-friendly architecture including programmable slew rate, drive strength, bushold, and programmable pull-up resistors Schmitt triggers enabling noise tolerant inputs (programmable per pin) I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz Supports hot-socketing Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 ISP circuitry compliant with IEEE Std. 1532
■ ■
■ ■
■ ■
■
October 2008
Altera Corporation
MAX II Device Handbook
http://www.xinpian.net
提供芯片解密,单片机解密程序破解服务
010-62245566
1–2
Chapter 1: Introduction Features
Table 1–1 shows the MAX II family features.
Table 1–1. MAX II Family Features Feature LEs Typical Equivalent Macrocells Equivalent Macrocell Range UFM Size (bits) Maximum User I/O pins tPD1 (ns) (1) fCNT (MHz) (2) tSU (ns) tCO (ns)
Notes to Table 1–1:
(1) tPD1 represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic implemented in a single LUT and LAB that is adjacent to the output pin. (2) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster than this number.
EPM240 EPM240G 240 192 128 to 240 8,192 80 4.7 304 1.7 4.3

上一页下一页