F28M35x Concerto? 微控制器

Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Concerto? 微微控控制制器器1器器件件概概要要1.1 特特性性1?主控子系统 — ARM? Cortex? -M3 ? 控制子系统 - TMS320Cf20;BACKGROUND-COLOR:#4ae2f7">28x 32 位CPU – 高达 100MHz – 高达 150MHz – Cortex-M3 内核硬件内置自检 – Cf20;BACKGROUND-COLOR:#4ae2f7">28x 内核硬件内置自检 – 嵌入式存储器 – 嵌入式存储器 ? 高达 512KB 闪存(纠错码 (ECC)) ? 高达 512KB 闪存(纠错码 (ECC)) ? 高达 32KB RAM(ECC 或奇偶校验) ? 高达 36KB RAM(ECC 或奇偶校验) ? 高达 64KB 共享 RAM ? 高达 64KB 共享 RAM ? 2KB 处理器间通信 (IPC) 消息 RAM ? 2KB 处理器间通信 (IPC) 消息 RAM – 5 个通用异步接收器/发射器 (UART) – IEEE-754 单精度浮点单元 (FPU) – 4 个同步串行接口 (SSI) 和串行外设接口 (SPI) – Viterbi,复杂数学运算,循环冗余校验 (CRC) 单元(VCU) – 2 个内部集成电路 (I2 C) – 串行通信接口 (SCI) – 通用串行总线如影随形 (USB-OTG) + 物理层 (PHY) – SPI – 10/100 以太网 (ENET) 1588 介质独立接口 (MII) – I2 C – 2 个控制器区域网 (CAN) – 6 通道直接内存访问(DMA) – 32 通道微直接内存访问 (?DMA) – 9 个增强型脉宽调制器 (ePWM) 模块 – 双重安全区域(每个区域 1f20;BACKGROUND-COLOR:#4ae2f7">28 位密码) ? 18 个输出(16 个为高分辨率) – 外设接口 (EPI) – 6 个32 位增强型捕捉 (eCAP) 模块 – 微循环冗余检验 (?CRC) 模块 – 3 个32 位增强型正交编码器脉冲 (eQEP) 模块 – 4 个通用定时器 – 多通道缓冲串行端口 (McBSP) – 2 个看门狗定时器模块 – EPI – 字节序:小端序 – 一个安全区域(1f20;BACKGROUND-COLOR:#4ae2f7">28 位密码) ? 计时 – 3 个32 位定时器 – 片上晶振振荡器和外部时钟输入 – 字节序:小端序 – 支持动态锁相环 (PLL) 比率变化 ? 模拟子系统 ? 1.2V 数字,1.8V 模拟,3.3V I/O 设计 – 双12 位模数转换器 (ADC) ? 处理器间通信 (IPC) – 高达 2.88MSPS – 32 个信号交换通道 – 高达 20 通道 – 4 个通道生成 IPC 中断 – 4 个采样保持 (S/H) 电路 – 可被用于通过 IPC 消息 RAM 协同数据传输 – 多达 6 个具有 10 位数模转换器 (DAC) 的比较器 ? 多达 74 个独立可编程、复用通用输入/输出 (I/O) 引?封装脚–144 引脚 RFP PowerPAD? 耐热增强型薄型四 – 无毛刺脉冲 I/O 方扁平封装 (HTQFP) 1 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. English Data Sheet: SPRS742 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 1.2 应应用用范范围围?伺服器驱动 ? 太阳能逆变器 ? 高端交流逆变器 ? 电动汽车/混合动力电动汽车 (EV/HEV) 充电器 ? 工业用不间断电源 (UPS) ? 电力线通信 1.3 说说明明Concerto 系列是一款多内核片上系统微控制器单元 (MCU),此控制器单元具有独立的通信和实时控制子系统. Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x 系列器件是 Concerto 产品中的第一系列产品. 此通信子系统基于行业标准 32 位ARM Cortex-M3 CPU,并且特有多种通信外设,其中包括以太网 1588, 具有 PHY 的USB OTG,CAN,UART,SSI,I2 C 和一个外部接口. 此实时控制子系统基于 TI 行业领先的私有 32 位Cf20;BACKGROUND-COLOR:#4ae2f7">28x 浮点 CPU,并且特有最灵活和高精度的控制外设, 其中包括具有故障保护功能的 ePWM,和编码器以及捕捉 - 所有这些外设均由 TI 的TMS320C2000? Piccolo? 和Delfino? 系列产品来执行. 此外,Cf20;BACKGROUND-COLOR:#4ae2f7">28-CPU 已经添加了执行高效 Viterbi,复杂算术运算,16 位快速傅里叶变换 (FFT) 和CRC 算法的 VCU 指令加速器. 共享一个高速模拟子系统和补充 RAM 内存,还有片上电压稳压和冗余计时电路. 安全考虑还包括纠错码 (ECC),奇偶校验和代码安全内存,以及辅助系统级工业安全认证的文档. 器器件件信信息息订订货货编编号号封封装装封封装装尺尺寸寸Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52CRFP HTQFP (144) 20.0mm x 20.0mm Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22CRFP HTQFP (144) 20.0mm x 20.0mm Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52CRFP HTQFP (144) 20.0mm x 20.0mm Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20BRFP HTQFP (144) 20.0mm x 20.0mm Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20BRFP HTQFP (144) 20.0mm x 20.0mm 2 器件概要版权 ? 2011–2014, Texas Instruments Incorporated Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 1.4 功功能能方方框框图图A. 某些外设不在 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35Mx 和Ff20;BACKGROUND-COLOR:#4ae2f7">28M35Ex 器件上提供. 图图1-1. 功功能能方方框框图图版权 ? 2011–2014, Texas Instruments Incorporated 器件概要 3 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 内内容容1器器件件概概要要.1 5.1 Absolute Maximum Ratings 107 1.1 特性 1 5.2 Handling Ratings.107 1.2 应用范围 2 5.3 Recommended Operating Conditions 108 1.3 说明 2 5.4 Electrical Characteristics.109 1.4 功能方框图 3 6 Electrical Specifications.110 2 修修订订历历史史记记录录.5 6.1 Current Consumption 110 3 Device Overview 7 6.2 Thermal Design Considerations 115 3.1 Device Characteristics.8 6.3 Timing Parameter Symbology 116 6.4 Clock Frequencies, Requirements, and 3.2 Memory Maps 11 Characteristics 117 3.3 Master Subsystem 21 6.5 Power Sequencing.120 3.4 Control Subsystem 27 6.6 Flash Timing – Master Subsystem 124 3.5 Analog Subsystem 31 6.7 Flash Timing – Control Subsystem 127 3.6 Master Subsystem NMIs 34 6.8 GPIO Electrical Data and Timing 130 3.7 Control Subsystem NMIs.34 6.9 External Interrupt Electrical Data and Timing...... 138 3.8 Resets 36 7 Peripheral Information and Timings 139 3.9 Internal Voltage Regulation and Power-On-Reset Functionality 41 7.1 Analog and Shared Peripherals.139 3.10 Input Clocks and PLLs 44 7.2 Master Subsystem Peripherals 175 3.11 Master Subsystem Clocking.54 7.3 Control Subsystem Peripherals 196 3.12 Control Subsystem Clocking 59 8 Device and Documentation Support.231 3.13 Analog Subsystem Clocking 62 8.1 Device Support.231 3.14 Shared Resources Clocking 62 8.2 Documentation Support.232 3.15 Loss of Input Clock (NMI Watchdog Function) ..... 62 8.3 Related Links 233 3.16 GPIOs and Other Pins 64 8.4 社区资源 233 3.17 Emulation/JTAG 80 8.5 Trademarks 233 3.18 Code Security Module.83 8.6 Electrostatic Discharge Caution 233 3.19 ?CRC Module 84 8.7 Glossary.233 4 Terminal Description 86 9 Mechanical Packaging and Orderable Information.234 4.1 Terminal Assignments 86 9.1 Thermal Data for RFP Package 234 4.2 Terminal Functions.87 9.2 Packaging Information 234 5 Device Operating Conditions.107 4 内容版权 ? 2011–2014, Texas Instruments Incorporated Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 2 修修订订历历史史记记录录NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 这个数据表的修订历史记录强调了使 SPRS742G 器件专用数据表变为一个 SPRS742H 修订版本所做的技术改变. 范范围围: : Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x 器件目前可在 Q 温度范围内运行(-40°C 至125°C,针对汽车应用的 Q100 认证). 请参考 Table 3-1. 已添加 Section 8.3,相关链接,提供到可用资源的快速访问. 请参见以下表格. 位位置置添添加加、、删删除除、、和和修修改改全局 ? Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x 器件目前可在 Q 温度范围内运行(-40°C 至125°C,针对汽车应用的 Q100 认证). 请参考 Table 3-1. ? 已将 "Sleeponexit" 位名称替换为 "SLEEPEXIT" 节1已将标题从 "Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x (Concerto?) MCUs" 更改为"器件概要" 节1.1 特性: ? 主控子系统 — ARM? Cortex?-M3: – 已添加"Cortex-M3 内核硬件内置自检" ? 控制子系统 - TMS320Cf20;BACKGROUND-COLOR:#4ae2f7">28x 32 位CPU – 已添加"Cf20;BACKGROUND-COLOR:#4ae2f7">28x 内核硬件内置自检" 节1.3 说明: ? 已添加"器件信息"表Table 3-2 已添加"Cortex-M3 和Cf20;BACKGROUND-COLOR:#4ae2f7">28x 内核可能的速度组合"表Section 3.3.2 已将部分标题从"Cortex?-M3 内核硬件逻辑内置自检 (LBIST)"更改为"Cortex-M3 内核硬件内置自检" Section 3.3.2 已更新"Cortex-M3 内核硬件内置自检"部分 Table 3-15 从NVIC 到Cortex-M3 的中断: ? 中断号 64:已将说明从 "CAN1 INT0" 更改为 "CAN0 INT0" ? 中断号 65:已将说明从 "CAN1 INT1" 更改为 "CAN0 INT1" Section 3.4.2 已将部分标题从"Cf20;BACKGROUND-COLOR:#4ae2f7">28x? 内核硬件逻辑内置自检 (LBIST)"更改为"Cf20;BACKGROUND-COLOR:#4ae2f7">28x 内核硬件内置自检" Section 3.4.2 已更新"Cf20;BACKGROUND-COLOR:#4ae2f7">28x 内核硬件内置自检"部分 Section 3.8 复位: ? 已更新对于 XRS 引脚的要求列表 Section 3.8.4 器件引导顺序: ? 已更新"引导模式 0、2、3、4、9、10 和12 被使用..."一段 Section 3.12.1 Cf20;BACKGROUND-COLOR:#4ae2f7">28x 正常模式: ? 已删除对 HISPCP 寄存器的引用 Figure 3-12 已更新"Cf20;BACKGROUND-COLOR:#4ae2f7">28x 时钟和低功率模式"图表 Table 4-1 端子功能: ? XCLKOUT:已更新说明已将 XCLKCFG 更改为 XPLLCLKCFG ? NC:已更新说明 Section 5.1 最大绝对额定值: ? 已添加电源斜升速率 (VDDIO,VDD18,VDD12,VDDA) Section 5.2 已添加"处理额定值"部分 Table 6-6 已添加"晶振等效串联电阻 (ESR) 要求"表Table 6-17 电源管理和监控电路解决方案: ? 已删除 TPS75005 Table 6-25 已添加"主控子系统 - 闪存数据保持持续时间"表Table 6-34 已添加"控制子系统 - 闪存数据保持持续时间"表Section 7.3.5 Cf20;BACKGROUND-COLOR:#4ae2f7">28x 串行通信接口: ? 已更新 SCI 模块特性列表: – 已将"4 级级发送和接收 FIFO"更改为"16 级级发送和接收 FIFO" 版权 ? 2011–2014, Texas Instruments Incorporated 修订历史记录 5 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 位位置置添添加加、、删删除除、、和和修修改改Section 8 器件和文档支持: ? 已添加 Section 8.3,相关链接 ? 已添加"商标"部分 ? 已添加"静电放电警告"部分 ? 已添加"术语表"部分 6 修订历史记录版权 ? 2011–2014, Texas Instruments Incorporated Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3 Device Overview The Concerto MCU comprises three subsystems: the Master Subsystem, the Control Subsystem, and the Analog Subsystem. While the Master and Control Subsystem each have dedicated local memories and peripherals, they can also share data and events through shared memories and peripherals. The Analog Subsystem has two ADC converters and six Analog Comparators. Both the Master and Control Subsystems access the Analog Subsystem through the Analog Common Interface Bus (ACIB). The NMI Blocks force communication of critical events to the Master and Control Subsystem processors and their Watchdog Timers. The Reset Block responds to Watchdog Timer NMI Reset, External Reset, and other events to initialize subsystem processors and the rest of the chip to a known state. The Clocking Blocks support multiple low-power modes where clocks to the processors and peripherals can be slowed down or stopped in order to manage power consumption. NOTE Throughout this document, the Master Subsystem is denoted by the color "blue"; the Control Subsystem is denoted by the color "green"; and the Analog Subsystem is denoted by the color "orange". Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 7 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.1 Device Characteristics Table 3-1 lists the features of the Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x devices. Table 3-1. Hardware Features FEATURE TYPE(1) H52C H22C M52C M22C M20B E20B Master Subsystem — ARM Cortex-M3 Speed (MHz)(2) – 100 100 75 75 75 60 Flash (KB) – 512 256 512 256 256 256 RAM ECC (KB) – 16 16 16 16 16 16 RAM Parity (KB) – 16 16 16 16 16 16 IPC Message RAM Parity (KB) – 2 2 2 2 2 2 Security Zones – 2 2 2 2 2 2 10/100 ENET 1588 MII 0 Yes Yes Yes Yes No No USB OTG FS 0 Yes Yes Yes Yes No No SSI/SPI 0 4 4 4 4 4 4 UART 0 5 5 5 5 5 5 I2 C 0 2 2 2 2 2 2 CAN 0 2 2 2 2 2 2 ?DMA 0 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch EPI 0 1 1 1 1 1 1 ?CRC module 0 1 1 1 1 1 1 General-Purpose Timers – 4 4 4 4 4 4 Watchdog Timer modules – 2 2 2 2 2 2 Control Subsystem — Cf20;BACKGROUND-COLOR:#4ae2f7">28x FPU/VCU Speed (MHz)(2) 150 150 75 75 75 60 Flash (KB) 512 256 512 256 256 256 RAM ECC (KB) 20 20 20 20 20 20 RAM Parity (KB) 16 16 16 16 16 16 IPC Message RAM Parity (KB) 2 2 2 2 2 2 Security Zones 1 1 1 1 1 1 8 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-1. Hardware Features (continued) FEATURE TYPE(1) H52C H22C M52C M22C M20B E20B ePWM modules 2 9: 18 outputs High-Resolution PWM (HRPWM) outputs 2 16 outputs eCAP modules/PWM outputs 0 6 (32-bit) eQEP modules 0 3 (32-bit) Fault Trip Zones – 12 on any of 64 GPIO pins McBSP/SPI 1 1 1 1 1 1 1 SCI 0 1 1 1 1 1 1 SPI 0 1 1 1 1 1 1 I2 C 0 1 1 1 1 1 1 DMA 0 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch EPI 0 1 1 1 1 1 1 32-Bit Timers – 3 3 3 3 3 3 Shared Supplemental RAM Parity (KB) 64 64 64 64 0 0 MSPS(3) 2.88 2.88 2.88 2.88 2.88 2.31 Conversion Time(3) 347 ns 347 ns 347 ns 347 ns 347 ns 433 ns 12-Bit ADC 1 3 Channels 10 10 10 10 10 10 Sample-and-Hold 2 2 2 2 2 2 MSPS(3) 2.88 2.88 2.88 2.88 2.88 2.31 Conversion Time(3) 347 ns 347 ns 347 ns 347 ns 347 ns 433 ns 12-Bit ADC 2 3 Channels 10 10 10 10 10 10 Sample-and-Hold 2 2 2 2 2 2 Comparators with Integrated DACs 0 6 6 6 6 6 6 Voltage Regulator Yes – Uses 3.3-V Single Supply (3.3-V/1.2-V recommended for 125?C) Clocking See Section 3.10 Additional Safety Master Subsystem 2 Watchdogs, NMI Watchdog: CPU, Memory Control Subsystem NMI Watchdog: CPU, Memory Shared Critical Register and I/O Function Lock Protection; RAM Fetch Protection Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 9 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-1. Hardware Features (continued) FEATURE TYPE(1) H52C H22C M52C M22C M20B E20B Packaging Package Type 144-Pin RFP PowerPAD HTQFP Available at Prototype Sampling T: –40°C to 105°C – Yes Yes Yes Yes Yes Yes Temperature options S: –40°C to 125°C – Yes Yes Yes Yes Yes Yes Q: –40°C to 125°C(4) – Yes Yes Yes Yes Yes Yes Product status(5) – Ff20;BACKGROUND-COLOR:#4ae2f7">28M35... Ff20;BACKGROUND-COLOR:#4ae2f7">28M35... Ff20;BACKGROUND-COLOR:#4ae2f7">28M35... Ff20;BACKGROUND-COLOR:#4ae2f7">28M35... Ff20;BACKGROUND-COLOR:#4ae2f7">28M35... Ff20;BACKGROUND-COLOR:#4ae2f7">28M35... (1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the TMS320xf20;BACKGROUND-COLOR:#4ae2f7">28xx, f20;BACKGROUND-COLOR:#4ae2f7">28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides. (2) The maximum frequency at which the Cortex-M3 core can run is 100 MHz. The clock divider before the Cortex-M3 core can only take values of /1, /2, or /4. For this reason, when the Cf20;BACKGROUND-COLOR:#4ae2f7">28x is configured to run at the maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex-M3 is 75 MHz. If the Cortex-M3 is configured to run at 100 MHz, the maximum frequency of the Cf20;BACKGROUND-COLOR:#4ae2f7">28x is limited to 100 MHz. (3) An integer divide ratio must be maintained between the Cf20;BACKGROUND-COLOR:#4ae2f7">28x and ADC clock frequencies. All MSPS and Conversion Time values are based on the maximum Cf20;BACKGROUND-COLOR:#4ae2f7">28x clock frequency. (4) "Q" refers to Q100 qualification for automotive applications. (5) The "Ff20;BACKGROUND-COLOR:#4ae2f7">28M35..." product status denotes a fully qualified production device. See Section 8.1.2, Device Nomenclature, for descriptions of device stages. Table 3-2. Possible Speed Combinations for Cortex-M3 and Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cores Cortex-M3 75 MHz 100 MHz 75 MHz 60 MHz Cf20;BACKGROUND-COLOR:#4ae2f7">28x 150 MHz 100 MHz 75 MHz 60 MHz 10 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.2 Memory Maps Section 3.2.1 shows the Control Subsystem Memory Map. Section 3.2.2 shows the Master Subsystem Memory Map. 3.2.1 Control Subsystem Memory Map Table 3-3. Control Subsystem M0, M1 RAM C Address Size C DMA Access(1) Control Subsystem M0, M1 RAM (x16 Aligned)(1) (Bytes) no 0000 0000 – 0000 03FF M0 RAM (ECC) 2K no 0000 0400 – 0000 07FF M1 RAM (ECC) 2K (1) The letter "C" refers to the Control Subsystem. Table 3-4. Control Subsystem Peripheral Frame 0 (Includes Analog) C Address Control Subsystem Peripheral Frame 0 Size C DMA Access(1) (x16 Aligned)(1) (Includes Analog) (Bytes) 0000 0800 – 0000 087F Reserved Control Subsystem Device Configuration Registers (Read no 0000 0880 – 0000 0890 34 Only) 0000 0891 – 0000 0ADF Reserved no 0000 0AE0 – 0000 0AEF Cf20;BACKGROUND-COLOR:#4ae2f7">28x CSM Registers 32 0000 0AF0 – 0000 0AFF Reserved yes 0000 0B00 – 0000 0B0F ADC1 Result Registers 32 0000 0B10 – 0000 0B3F Reserved yes 0000 0B40 – 0000 0B4F ADC2 Result Registers 32 0000 0B50 – 0000 0BFF Reserved no 0000 0C00 – 0000 0C07 CPU Timer 0 16 no 0000 0C08 – 0000 0C0F CPU Timer 1 16 no 0000 0C10 – 0000 0C17 CPU Timer 2 16 0000 0C18 – 0000 0CDF Reserved no 0000 0CE0 – 0000 0CFF PIE Registers 64 no 0000 0D00 – 0000 0DFF PIE Vector Table 512 no 0000 0E00 – 0000 0EFF PIE Vector Table Copy (Read Only) 512 0000 0F00 – 0000 0FFF Reserved no 0000 1000 – 0000 11FF Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA Registers 1K 0000 1200 – 0000 16FF Reserved no 0000 1700 – 0000 177F Analog Subsystem Control Registers 256 no 0000 1780 – 0000 17FF C Hardware Logic BIST Registers 256 0000 1800 – 0000 3FFF Reserved (1) The letter "C" refers to the Control Subsystem. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 11 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-5. Control Subsystem Peripheral Frame 3 C Address Control Subsystem Size M Address ?DMA C DMA Access(1) (x16 Aligned)(1) Peripheral Frame 3 (Bytes) (Byte-Aligned)(2) Access no 0000 4000 – 0000 4181 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Flash Control Registers 772 0000 4182 – 0000 42FF Reserved Cf20;BACKGROUND-COLOR:#4ae2f7">28x Flash ECC Error Log no 0000 4300 – 0000 4323 72 Registers 0000 4324 – 0000 43FF Reserved no 0000 4400 – 0000 443F M Clock Control Registers(2) 1f20;BACKGROUND-COLOR:#4ae2f7">28 400F B800 – 400F B87F no 0000 4440 – 0000 48FF Reserved no 0000 4900 – 0000 497F RAM Configuration Registers 256 400F B200 – 400F B2FF no 0000 4980 – 0000 49FF Reserved RAM ECC/Parity/Access Error no 0000 4A00 – 0000 4A7F 256 400F B300 – 400F B3FF no Log Registers 0000 4A80 – 0000 4DFF Reserved no 0000 4E00 – 0000 4E3F CtoM and MtoC IPC Registers 1f20;BACKGROUND-COLOR:#4ae2f7">28 400F B700 – 400F B77F no 0000 4E40 – 0000 4FFF Reserved yes 0000 5000 – 0000 503F McBSP-A 1f20;BACKGROUND-COLOR:#4ae2f7">28 0000 5040 – 0000 50FF Reserved yes 0000 5100 – 0000 517F EPWM1 (Hi-Resolution) 256 yes 0000 5180 – 0000 51FF EPWM2 (Hi-Resolution) 256 yes 0000 5200 – 0000 527F EPWM3 (Hi-Resolution) 256 yes 0000 5f20;BACKGROUND-COLOR:#4ae2f7">280 – 0000 52FF EPWM4 (Hi-Resolution) 256 yes 0000 5300 – 0000 537F EPWM5 (Hi-Resolution) 256 yes 0000 5380 – 0000 53FF EPWM6 (Hi-Resolution) 256 yes 0000 5400 – 0000 547F EPWM7 (Hi-Resolution) 256 yes 0000 5480 – 0000 54FF EPWM8 (Hi-Resolution) 256 yes 0000 5500 – 0000 557F EPWM9 256 0000 5580 – 0000 57FF Reserved (1) The letter "C" refers to the Control Subsystem. (2) The letter "M" refers to the Master Subsystem. 12 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-6. Control Subsystem Peripheral Frame 1 C Address Size C DMA Access(1) Control Subsystem Peripheral Frame 1 (x16 Aligned)(1) (Bytes) 0000 5800 – 0000 59FF Reserved no 0000 5A00 – 0000 5A1F ECAP1 64 no 0000 5A20 – 0000 5A3F ECAP2 64 no 0000 5A40 – 0000 5A5F ECAP3 64 no 0000 5A60 – 0000 5A7F ECAP4 64 no 0000 5A80 – 0000 5A9F ECAP5 64 no 0000 5AA0 – 0000 5ABF ECAP6 64 0000 5AC0 – 0000 5AFF Reserved no 0000 5B00 – 0000 5B3F EQEP1 1f20;BACKGROUND-COLOR:#4ae2f7">28 no 0000 5B40 – 0000 5B7F EQEP2 1f20;BACKGROUND-COLOR:#4ae2f7">28 no 0000 5B80 – 0000 5BBF EQEP3 1f20;BACKGROUND-COLOR:#4ae2f7">28 0000 5BC0 – 0000 5F7F Reserved no 0000 5F80 – 0000 5FFF C GPIO Group 1 Registers(1) 256 0000 6000 – 0000 63FF Reserved no 0000 6400 – 0000 641F COMP1 Registers 64 no 0000 6420 – 0000 643F COMP2 Registers 64 no 0000 6440 – 0000 645F COMP3 Registers 64 no 0000 6460 – 0000 647F COMP4 Registers 64 no 0000 6480 – 0000 649F COMP5 Registers 64 no 0000 64A0 – 0000 64BF COMP6 Registers 64 0000 64C0 – 0000 6F7F Reserved no 0000 6F80 – 0000 6FFF C GPIO Group 2 Registers and AIO Mux Registers(1) 256 (1) The letter "C" refers to the Control Subsystem. Table 3-7. Control Subsystem Peripheral Frame 2 C Address Size C DMA Access(1) Control Subsystem Peripheral Frame 2 (x16 Aligned)(1) (Bytes) 0000 7000 – 0000 70FF Reserved no 0000 7010 – 0000 702F Cf20;BACKGROUND-COLOR:#4ae2f7">28x System Control Registers 64 0000 7030 – 0000 703F Reserved no 0000 7040 – 0000 704F SPI-A 32 no 0000 7050 – 0000 705F SCI-A 32 no 0000 7060 – 0000 706F NMI Watchdog Interrupt Registers 32 no 0000 7070 – 0000 707F External Interrupt Registers 32 0000 7080 – 0000 70FF Reserved ADC1 Configuration Registers no 0000 7100 – 0000 717F 256 (Only 16-bit read/write access supported) ADC2 Configuration Registers no 0000 7180 – 0000 71FF 256 (Only 16-bit read/write access supported) 0000 7200 – 0000 78FF Reserved no 0000 7900 – 0000 793F I2C-A 1f20;BACKGROUND-COLOR:#4ae2f7">28 0000 7940 – 0000 7FFF Reserved (1) The letter "C" refers to the Control Subsystem. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 13 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-8. Control Subsystem RAMs C Address Size M Address ?DMA C DMA Access(1) Control Subsystem RAMs (x16 Aligned)(1) (Bytes) (Byte-Aligned)(2) Access no 0000 8000 – 0000 8FFF L0 RAM (ECC, Secure) 8K no 0000 9000 – 0000 9FFF L1 RAM (ECC, Secure) 8K yes 0000 A000 – 0000 AFFF L2 RAM (Parity, Interleaving) 8K yes 0000 B000 – 0000 BFFF L3 RAM (Parity, Interleaving) 8K yes 0000 C000 – 0000 CFFF S0 RAM (Parity, Shared) 8K 2000 8000 – 2000 9FFF yes yes 0000 D000 – 0000 DFFF S1 RAM (Parity, Shared) 8K 2000 A000 – 2000 BFFF yes yes 0000 E000 – 0000 EFFF S2 RAM (Parity, Shared) 8K 2000 C000 – 2000 DFFF yes yes 0000 F000 – 0000 FFFF S3 RAM (Parity, Shared) 8K 2000 E000 – 2000 FFFF yes yes 0001 0000 – 0001 0FFF S4 RAM (Parity, Shared) 8K 2001 0000 – 2001 1FFF yes yes 0001 1000 – 0001 1FFF S5 RAM (Parity, Shared) 8K 2001 2000 – 2001 3FFF yes yes 0001 2000 – 0001 2FFF S6 RAM (Parity, Shared) 8K 2001 4000 – 2001 5FFF yes yes 0001 3000 – 0001 3FFF S7 RAM (Parity, Shared) 8K 2001 6000 – 2001 7FFF yes 0001 4000 – 0003 F7FF Reserved yes yes 0003 F800 – 0003 FBFF CtoM MSG RAM (Parity) 2K 2007 F000 – 2007 F7FF read only yes 0003 FC00 – 0003 FFFF MtoC MSG RAM (Parity) 2K 2007 F800 – 2007 FFFF yes read only 0004 0000 – 0004 7FFF Reserved no 0004 8000 – 0004 8FFF L0 RAM - ECC Bits 8K no 0004 9000 – 0004 9FFF L1 RAM - ECC Bits 8K no 0004 A000 – 0004 AFFF L2 RAM - Parity Bits 8K no 0004 B000 – 0004 BFFF L3 RAM - Parity Bits 8K no 0004 C000 – 0004 CFFF S0 RAM - Parity Bits 8K 2008 8000 – 2008 9FFF no no 0004 D000 – 0004 DFFF S1 RAM - Parity Bits 8K 2008 A000 – 2008 BFFF no no 0004 E000 – 0004 EFFF S2 RAM - Parity Bits 8K 2008 C000 – 2008 DFFF no no 0004 F000 – 0004 FFFF S3 RAM - Parity Bits 8K 2008 E000 – 2008 FFFF no no 0005 0000 – 0005 0FFF S4 RAM - Parity Bits 8K 2009 0000 – 2009 1FFF no no 0005 1000 – 0005 1FFF S5 RAM - Parity Bits 8K 2009 2000 – 2009 3FFF no no 0005 2000 – 0005 2FFF S6 RAM - Parity Bits 8K 2009 4000 – 2009 5FFF no no 0005 3000 – 0005 3FFF S7 RAM - Parity Bits 8K 2009 6000 – 2009 7FFF no 0005 4000 – 0007 EFFF Reserved no 0007 F000 – 0007 F3FF M0 RAM - ECC Bits 2K no 0007 F400 – 0007 F7FF M1 RAM - ECC Bits 2K no 0007 F800 – 0007 FBFF CtoM MSG RAM - Parity Bits 2K 200F F000 – 200F F7FF no no 0007 FC00 – 0007 FFFF MtoC MSG RAM - Parity Bits 2K 200F F800 – 200F FFFF no 0008 0000 – 0009 FFFF Reserved (1) The letter "C" refers to the Control Subsystem. (2) The letter "M" refers to the Master Subsystem. 14 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-9. Control Subsystem Flash, ECC, OTP, Boot ROM C Address Control Subsystem Size M Address ?DMA C DMA Access(1) (x16 Aligned)(1) Flash, ECC, OTP, Boot ROM (Bytes) (Byte-Aligned)(2) Access Sector N (not available for no 0010 0000 – 0010 1FFF 16K 256KB Flash configuration) Sector M (not available for no 0010 2000 – 0010 3FFF 16K 256KB Flash configuration) Sector L (not available for no 0010 4000 – 0010 5FFF 16K 256KB Flash configuration) Sector K (not available for no 0010 6000 – 0010 7FFF 16K 256KB Flash configuration) Sector J (not available for no 0010 8000 – 0010 FFFF 64K 256KB Flash configuration) Sector I (not available for no 0011 0000 – 0011 7FFF 64K 256KB Flash configuration) Sector H (not available for no 0011 8000 – 0011 FFFF 64K 256KB Flash configuration) no 0012 0000 – 0012 7FFF Sector G 64K no 0012 8000 – 0012 FFFF Sector F 64K no 0013 0000 – 0013 7FFF Sector E 64K no 0013 8000 – 0013 9FFF Sector D 16K no 0013 A000 – 0013 BFFF Sector C 16K no 0013 C000 – 0013 DFFF Sector B 16K Sector A no 0013 E000 – 0013 FFFF (CSM password in the high 16K address) 0014 0000 – 001F FFFF Reserved Flash - ECC Bits no 0020 0000 – 0020 7FFF 64K (1/8 of Flash used = 64 KBytes) 0020 8000 – 0024 01FF Reserved TI one-time programmable no 0024 0200 – 0024 03FF 1K (OTP) memory 0024 0400 – 002F FFFF Reserved EPI0 yes 0030 0000 – 003F 7FFF (External Peripheral/Memory 2G 6000 0000 – DFFF FFFF yes Interface)(3) no 003F 8000 – 003F FFFF Cf20;BACKGROUND-COLOR:#4ae2f7">28x Boot ROM (64 KBytes) 64K (1) The letter "C" refers to the Control Subsystem. (2) The letter "M" refers to the Master Subsystem. (3) The Control Subsystem has no direct access to EPI in silicon revision 0 devices. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 15 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.2.2 Master Subsystem Memory Map Table 3-10. Master Subsystem Flash, ECC, OTP, Boot ROM M Address Size ?DMA Access Master Subsystem Flash, ECC, OTP, Boot ROM (Byte-Aligned)(1) (Bytes) Boot ROM - Dual-mapped to 0x0100 0000 no 0000 0000 – 0000 FFFF 64K (Both maps access same physical location.) 0001 0000 – 001F FFFF Reserved Sector N no 0020 0000 – 0020 3FFF 16K (Zone 1 CSM password in the low address.) no 0020 4000 – 0020 7FFF Sector M 16K no 0020 8000 – 0020 BFFF Sector L 16K no 0020 C000 – 0020 FFFF Sector K 16K no 0021 0000 – 0021 FFFF Sector J 64K no 0022 0000 – 0022 FFFF Sector I (not available for 256KB Flash configuration) 64K no 0023 0000 – 0023 FFFF Sector H (not available for 256KB Flash configuration) 64K no 0024 0000 – 0024 FFFF Sector G (not available for 256KB Flash configuration) 64K no 0025 0000 – 0025 FFFF Sector F (not available for 256KB Flash configuration) 64K no 0026 0000 – 0026 FFFF Sector E 64K no 0027 0000 – 0027 3FFF Sector D 16K no 0027 4000 – 0027 7FFF Sector C 16K no 0027 8000 – 0027 BFFF Sector B 16K Sector A no 0027 C000 – 0027 FFFF 16K (Zone 2 CSM password in the high address.) 00f20;BACKGROUND-COLOR:#4ae2f7">28 0000 – 005F FFFF Reserved Flash - ECC Bits no 0060 0000 – 0060 FFFF 64K (1/8 of Flash used = 64 KBytes) 0061 0000 – 0068 047F Reserved no 0068 0480 – 0068 07FF TI OTP 896 no 0068 0800 OTP – Security Lock 4 0068 0804 Reserved 0068 0808 Reserved no 0068 080C OTP – Zone 2 Flash Start Address 4 no 0068 0810 OTP – Ethernet Media Access Controller (EMAC) Address 0 4 no 0068 0814 OTP – EMAC Address 1 4 0068 0818 – 0070 00FF Reserved OTP – ECC Bits – Application Use no 0070 0100 – 0070 0102 3 (1/8 of OTP used = 3 Bytes) 0070 0103 – 00FF FFFF Reserved Boot ROM – Dual-mapped to 0x0000 0000 no 0100 0000 – 0100 FFFF 64K (Both maps access same physical location.) 0101 0000 – 03FF FFFF Reserved ROM/Flash/OTP/Boot ROM – Mirror-mapped for ?CRC. Accessing this area of memory by the ?CRC peripheral will cause an access in 0000 0000 – 03FF FFFF memory space. Mirrored boot ROM: 0x0400 0000 – 0x0400 FFFF (Not dual-mapped ROM address) no 0400 0000 – 07FF FFFF 64M Mirrored Flash bank: 0x0420 0000 – 0x042F FFFF Mirrored Flash OTP: 0x0468 0000 – 0x0468 1FFF (Read cycles from this space cause the ?CRC peripheral to continuously update data checksum inside a register, when reading a block of data.) 0800 0000 – 1FFF FFFF Reserved (1) The letter "M" refers to the Master Subsystem. 16 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-11. Master Subsystem RAMs ?DMA M Address Size C Address Master Subsystem RAMs C DMA Access(2) Access (Byte-Aligned)(1) (Bytes) (x16 Aligned)(2) no 2000 0000 – 2000 1FFF C0 RAM (ECC, Secure) 8K no 2000 2000 – 2000 3FFF C1 RAM (ECC, Secure) 8K yes 2000 4000 – 2000 5FFF C2 RAM (Parity) 8K yes 2000 6000 – 2000 7FFF C3 RAM (Parity) 8K yes 2000 8000 – 2000 9FFF S0 RAM (Parity, Shared) 8K 0000 C000 – 0000 CFFF yes yes 2000 A000 – 2000 BFFF S1 RAM (Parity, Shared) 8K 0000 D000 – 0000 DFFF yes yes 2000 C000 – 2000 DFFF S2 RAM (Parity, Shared) 8K 0000 E000 – 0000 EFFF yes yes 2000 E000 – 2000 FFFF S3 RAM (Parity, Shared) 8K 0000 F000 – 0000 FFFF yes yes 2001 0000 – 2001 1FFF S4 RAM (Parity, Shared) 8K 0001 0000 – 0001 0FFF yes yes 2001 2000 – 2001 3FFF S5 RAM (Parity, Shared) 8K 0001 1000 – 0001 1FFF yes yes 2001 4000 – 2001 5FFF S6 RAM (Parity, Shared) 8K 0001 2000 – 0001 2FFF yes yes 2001 6000 – 2001 7FFF S7 RAM (Parity, Shared) 8K 0001 3000 – 0001 3FFF yes 2001 8000 – 2007 EFFF Reserved yes 2007 F000 – 2007 F7FF CtoM MSG RAM (Parity) 2K 0003 F800 – 0003 FBFF yes read only yes yes 2007 F800 – 2007 FFFF MtoC MSG RAM (Parity) 2K 0003 FC00 – 0003 FFFF read only no 2008 0000 – 2008 1FFF C0 RAM - ECC Bits 8K no 2008 2000 – 2008 3FFF C1 RAM - ECC Bits 8K no 2008 4000 – 2008 5FFF C2 RAM - Parity Bits 8K no 2008 6000 – 2008 7FFF C3 RAM - Parity Bits 8K no 2008 8000 – 2008 9FFF S0 RAM - Parity Bits 8K 0004 C000 – 0004 CFFF no no 2008 A000 – 2008 BFFF S1 RAM - Parity Bits 8K 0004 D000 – 0004 DFFF no no 2008 C000 – 2008 DFFF S2 RAM - Parity Bits 8K 0004 E000 – 0004 EFFF no no 2008 E000 – 2008 FFFF S3 RAM - Parity Bits 8K 0004 F000 – 0004 FFFF no no 2009 0000 – 2009 1FFF S4 RAM - Parity Bits 8K 0005 0000 – 0005 0FFF no no 2009 2000 – 2009 3FFF S5 RAM - Parity Bits 8K 0005 1000 – 0005 1FFF no no 2009 4000 – 2009 5FFF S6 RAM - Parity Bits 8K 0005 2000 – 0005 2FFF no no 2009 6000 – 2009 7FFF S7 RAM - Parity Bits 8K 0005 3000 – 0005 3FFF no 2009 8000 – 200F EFFF Reserved no 200F F000 – 200F F7FF CtoM MSG RAM - Parity Bits 2K 0007 F800 – 0007 FBFF no no 200F F800 – 200F FFFF MtoC MSG RAM - Parity Bits 2K 0007 FC00 – 0007 FFFF no 2010 0000 – 21FF FFFF Reserved Bit Banded RAM Zone (Dedicated address for each yes 2200 0000 – 23FF FFFF 32M RAM bit of Cortex-M3 RAM blocks above) All RAM Spaces – Mirror- Mapped for ?CRC. Accessing this memory by the ?CRC peripheral will cause an access to 2000 0000 – 23FF FFFF yes 2400 0000 – 27FF FFFF 64M memory space. (Read cycles from this space cause the ?CRC peripheral to continuously update data checksum inside a register when reading a block of data.) f20;BACKGROUND-COLOR:#4ae2f7">2800 0000 – 3FFF FFFF Reserved (1) The letter "M" refers to the Master Subsystem. (2) The letter "C" refers to the Control Subsystem. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 17 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-12. Master Subsystem Peripherals ?DMA M Address Master Subsystem Size C Address C DMA Access(2) Access (Byte-Aligned)(1) Peripherals (Bytes) (x16 Aligned)(2) yes 4000 0000 – 4000 0FFF Watchdog Timer 0 Registers 4K yes 4000 1000 – 4000 1FFF Watchdog Timer 1 Registers 4K 4000 2000 – 4000 3FFF Reserved yes 4000 4000 – 4000 4FFF M GPIO Port A (APB Bus)(1) 4K yes 4000 5000 – 4000 5FFF M GPIO Port B (APB Bus)(1) 4K yes 4000 6000 – 4000 6FFF M GPIO Port C (APB Bus)(1) 4K yes 4000 7000 – 4000 7FFF M GPIO Port D (APB Bus)(1) 4K yes 4000 8000 – 4000 8FFF SSI0 4K yes 4000 9000 – 4000 9FFF SSI1 4K yes 4000 A000 – 4000 AFFF SSI2 4K yes 4000 B000 – 4000 BFFF SSI3 4K yes 4000 C000 – 4000 CFFF UART0 4K yes 4000 D000 – 4000 DFFF UART1 4K yes 4000 E000 – 4000 EFFF UART2 4K yes 4000 F000 – 4000 FFFF UART3 4K yes 4001 0000 – 4001 0FFF UART4 4K 4001 1000 – 4001 FFFF Reserved no 4002 0000 – 4002 07FF I2C0 Master 2K no 4002 0800 – 4002 0FFF I2C0 Slave 2K no 4002 1000 – 4002 17FF I2C1 Master 2K no 4002 1800 – 4002 1FFF I2C1 Slave 2K 4002 2000 – 4002 3FFF Reserved yes 4002 4000 – 4002 4FFF M GPIO Port E (APB Bus)(1) 4K yes 4002 5000 – 4002 5FFF M GPIO Port F (APB Bus)(1) 4K yes 4002 6000 – 4002 6FFF M GPIO Port G (APB Bus)(1) 4K yes 4002 7000 – 4002 7FFF M GPIO Port H (APB Bus)(1) 4K 4002 8000 – 4002 FFFF Reserved yes 4003 0000 – 4003 0FFF GP Timer 0 4K yes 4003 1000 – 4003 1FFF GP Timer 1 4K yes 4003 2000 – 4003 2FFF GP Timer 2 4K yes 4003 3000 – 4003 3FFF GP Timer 3 4K 4003 4000 – 4003 CFFF Reserved yes 4003 D000 – 4003 DFFF M GPIO Port J (APB Bus)(1) 4K 4003 E000 – 4003 FFFF Reserved yes 4004 8000 – 4004 8FFF ENET MAC0 4K 4004 9000 – 4004 FFFF Reserved yes 4005 0000 – 4005 0FFF USB MAC0 4K 4005 1000 – 4005 7FFF Reserved yes 4005 8000 – 4005 8FFF M GPIO Port A (AHB Bus)(1) 4K yes 4005 9000 – 4005 9FFF M GPIO Port B (AHB Bus)(1) 4K yes 4005 A000 – 4005 AFFF M GPIO Port C (AHB Bus)(1) 4K yes 4005 B000 – 4005 BFFF M GPIO Port D (AHB Bus)(1) 4K yes 4005 C000 – 4005 CFFF M GPIO Port E (AHB Bus)(1) 4K yes 4005 D000 – 4005 DFFF M GPIO Port F (AHB Bus)(1) 4K yes 4005 E000 – 4005 EFFF M GPIO Port G (AHB Bus)(1) 4K (1) The letter "M" refers to the Master Subsystem. (2) The letter "C" refers to the Control Subsystem. 18 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-12. Master Subsystem Peripherals (continued) ?DMA M Address Master Subsystem Size C Address C DMA Access(2) Access (Byte-Aligned)(1) Peripherals (Bytes) (x16 Aligned)(2) yes 4005 F000 – 4005 FFFF M GPIO Port H (AHB Bus)(1) 4K yes 4006 0000 – 4006 0FFF M GPIO Port J (AHB Bus)(1) 4K 4006 1000 – 4006 FFFF Reserved no 4007 0000 – 4007 3FFF CAN0 16K no 4007 4000 – 4007 7FFF CAN1 16K 4007 8000 – 400C FFFF Reserved no 400D 0000 – 400D 0FFF EPI0 (Registers only) 4K 400D 1000 – 400F 9FFF Reserved no 400F A000 – 400F A303 M Flash Control Registers(1) 772 400F A304 – 400F A5FF Reserved M Flash ECC Error Log no 400F A600 – 400F A647 72 Registers(1) 400F A648 – 400F AFFF Reserved no 400F B000 – 400F B1FF PBIST Control Registers 512 no 400F B200 – 400F B2FF RAM Configuration Registers 256 0000 4900 – 0000 497F no RAM ECC/Parity/Access Error no 400F B300 – 400F B3FF 256 0000 4A00 – 0000 4A7F no Log Registers no 400F B400 – 400F B5FF M CSM Registers(1) 512 no 400F B600 – 400F B67F ?CRC 1f20;BACKGROUND-COLOR:#4ae2f7">28 400F B680 – 400F B6FF Reserved no 400F B700 – 400F B77F CtoM and MtoC IPC Registers 1f20;BACKGROUND-COLOR:#4ae2f7">28 0000 4E00 – 0000 4E3F no 400F B780 – 400F B7FF Reserved no 400F B800 – 400F B87F M Clock Control Registers(1) 1f20;BACKGROUND-COLOR:#4ae2f7">28 0000 4400 – 0000 443F no no 400F B880 – 400F B8BF M LPM Control Registers(1) 64 no 400F B8C0 – 400F B8FF M Reset Control Registers(1) 64 0000 0880 – 0000 0890 no 400F B900 – 400F B93F Device Configuration Registers 64 (Read Only) 400F B940 – 400F B97F Reserved no 400F B980 – 400F B9FF M Write Protect Registers(1) 1f20;BACKGROUND-COLOR:#4ae2f7">28 no 400F BA00 – 400F BA7F M NMI Registers(1) 1f20;BACKGROUND-COLOR:#4ae2f7">28 400F BA80 – 400F BAFF Reserved no 400F BB00 – 400F BBFF M HWBIST Registers 256 400F BC00 – 400F EFFF Reserved no 400F F000 – 400F FFFF ?DMA Registers 4K 4010 0000 – 41FF FFFF Reserved Bit Banded Peripheral Zone (Dedicated address for each yes 4200 0000 – 43FF FFFF 32M register bit of Cortex-M3 peripherals above.) 4400 0000 – 4FFF FFFF Reserved Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 19 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-13. Master Subsystem Analog and EPI ?DMA M Address Master Subsystem Size C Address C DMA Access(2) Access (Byte-Aligned)(1) Analog and EPI (Bytes) (x16 Aligned)(2) 5000 0000 – 5000 15FF Reserved yes 5000 1600 – 5000 161F ADC1 Result Registers 32 5000 1620 – 5000 167F Reserved yes 5000 1680 – 5000 169F ADC2 Result Registers 32 5000 16A0 – 5FFF FFFF Reserved EPI0 yes 6000 0000 – DFFF FFFF (External Peripheral/Memory 2G 0030 0000 – 003F 7FFF(3) yes Interface) (1) The letter "M" refers to the Master Subsystem. (2) The letter "C" refers to the Control Subsystem. (3) The Control Subsystem has no direct access to EPI in silicon revision 0 devices. Table 3-14. Cortex-M3 Private Bus ?DMA Cortex-M3 Address Size Cortex-M3 Private Bus Access (Byte-Aligned) (Bytes) no E000 0000 – E000 0FFF ITM (Instrumentation Trace Macrocell) 4K no E000 1000 – E000 1FFF DWT (Data Watchpoint and Trace) 4K no E000 2000 – E000 2FFF FPB (Flash Patch and Breakpoint) 4K E000 3000 – E000 E007 Reserved no E000 E008 – E000 E00F System Control Block 8 no E000 E010 – E000 E01F System Timer 16 E000 E020 – E000 E0FF Reserved no E000 E100 – E000 E4EF Nested Vectored Interrupt Controller (NVIC) 1008 E000 E4F0 – E000 ECFF Reserved no E000 ED00 – E000 ED3F System Control Block 64 E000 ED40 – E000 ED8F Reserved no E000 ED90 – E000 EDB8 Memory Protection Unit 41 E000 EDB9 – E000 EEFF Reserved no E000 EF00 – E000 EF03 Nested Vectored Interrupt Controller 4 E000 EF04 – FFFF FFFF Reserved NOTE MPU is not available on silicon revision 0 devices. 20 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.3 Master Subsystem The Master Subsystem includes the Cortex-M3 CPU, ?DMA, Nested Vectored Interrupt Controller (NVIC), Cortex-M3 Peripherals, and Local Memory. Additionally, the Cortex-M3 CPU and ?DMA can access the Control Subsystem through Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and read ADC Result Registers via the Analog Common Interface Bus. The Master Subsystem can also receive events from the NMI block and send events to the Resets block. Figure 3-1 shows the Master Subsystem. 3.3.1 Cortex-M3 CPU The 32-bit Cortex-M3 processor offers high performance, fast interrupt handling, and access to a variety of communication peripherals (including Ethernet and USB). The Cortex-M3 features a Memory Protection Unit (MPU) to provide a privileged mode for protected operating system functionality. A bus bridge adjacent to the MPU can route program instructions and data on the I-CODE and D-CODE buses that connect to the Boot ROM and Flash. Other data is typically routed through the Cortex-M3 System Bus connected to the local RAMs. The System Bus also goes to the Shared Resources block (also accessible by the Control Subsystem) and to the Analog Subsystem through the ACIB. Another bus bridge allows bus cycles from both the Cortex-M3 System Bus and those of the ?DMA bus to access the Master Subsystem peripherals (via the APB bus or the AHP bus). Most of the interrupts to the Cortex-M3 CPU come from the NVIC, which manages the interrupt requests from peripherals and assigns handling priorities. There are also several exceptions generated by Cortex- M3 CPU that can return to the Cortex-M3 as interrupts after being prioritized with other requests inside the NVIC. In addition to programmable priority interrupts, there are also three levels of fixed-priority interrupts of which the highest priority, level-3, is given to M3PORRST and M3SYSRST resets from the Resets block. The next highest priority, level-2, is assigned to the M3NMIINT, which originates from the NMI block. The M3HRDFLT (Hard Fault) interrupt is assigned to level-1 priority, and this interrupt is caused by one of the error condition exceptions (Memory Management, Bus Fault, Usage Fault) escalating to Hard Fault because they are not enabled or not properly serviced. The Cortex-M3 CPU has two low-power modes: Sleep and Deep Sleep. 3.3.2 Cortex-M3 Core Hardware Built-In Self-Test The Concerto microcontroller Cortex-M3 CPU core includes a hardware built-in self-test (HWBIST) controller for testing the CPU core logic for errors. Tests are initiated by software whenever convenient (at start-up, idle, and so on), which allows for periodic logic tests to ensure that the CPU core logic is working correctly. During a test cycle, all interrupts are logged by the HWBIST controller and re-issued after the test cycle completes to ensure that no interrupts are missed. In the event of a logic error, the HWBIST controller generates an NMI on both cores to signal that an error has been detected. This action allows for the software to gracefully handle any detected logic errors. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 21 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 3-1. Master Subsystem 22 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.3.3 Cortex-M3 DMA and NVIC The Cortex-M3 direct memory access (?DMA) module provides a hardware method of transferring data between peripherals, between memory, and between peripherals and memory without intervention from the Cortex-M3 CPU. The NVIC manages and prioritizes interrupt handling for the Cortex-M3 CPU. The Cortex-M3 peripherals use REQ/DONE handshaking to coordinate data transfer requests with the ?DMA. If a DMA channel is enabled for a given peripheral, REQ/DONE from the peripheral will trigger the data transfer, following which an IRQ request may be sent from the ?DMA to the NVIC to announce to the Cortex-M3 that the transfer has completed. If a DMA channel is not enabled for a given peripheral, REQ/DONE will directly drive IRQ to the NVIC so that the Cortex-M3 CPU can transfer the data. For those peripherals that are not supported by the ?DMA, IRQs are supplied directly to the NVIC, bypassing the DMA. This case is true for both Watchdogs, CANs, I2 Cs, and the Analog-to-Digital Converters sending ADCINT[8:1] interrupts from the Analog Subsystem. The NMI Watchdog does not send any events to the ?DMA or the NVIC (only to the Resets block). 3.3.4 Cortex-M3 Interrupts Table 3-15 shows all interrupt assignments for the Cortex-M3 processor. Most interrupts (16–107) are associated with interrupt requests from Cortex-M3 peripherals. The first 15 interrupts (1–15) are processor exceptions generated by the Cortex-M3 core itself. These processor exceptions are detailed in Table 3-16. Table 3-15. Interrupts from NVIC to Cortex-M3 Interrupt Number Vector Number Vector Address or Offset Description (Bit in Interrupt Registers) – 0–15 0x0000.0000–0x0000.003C Processor exceptions 0 16 0x0000.0040 GPIO Port A 1 17 0x0000.0044 GPIO Port B 2 18 0x0000.0048 GPIO Port C 3 19 0x0000.004C GPIO Port D 4 20 0x0000.0050 GPIO Port E 5 21 0x0000.0054 UART0 6 22 0x0000.0058 UART1 7 23 0x0000.005C SSI0 8 24 0x0000.0060 I2C0 9–17 25–33 – Reserved 18 34 0x0000.0088 Watchdog Timers 0 and 1 19 35 0x0000.008C Timer 0A 20 36 0x0000.0090 Timer 0B 21 37 0x0000.0094 Timer 1A 22 38 0x0000.0098 Timer 1B 23 39 0x0000.009C Timer 2A 24 40 0x0000.00A0 Timer 2B 25–27 41–43 – Reserved f20;BACKGROUND-COLOR:#4ae2f7">28 44 0x0000.00B0 System Control 29 45 0x0000.00B4 Reserved 30 46 0x0000.00B8 GPIO Port F 31 47 0x0000.00BC GPIO Port G 32 48 0x0000.00C0 GPIO Port H 33 49 0x0000.00C4 UART2 34 50 0x0000.00C8 SSI1 35 51 0x0000.00CC Timer 3A 36 52 0x0000.00D0 Timer 3B Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 23 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-15. Interrupts from NVIC to Cortex-M3 (continued) Interrupt Number Vector Number Vector Address or Offset Description (Bit in Interrupt Registers) 37 53 0x0000.00D4 I2C1 38–41 54–57 – Reserved 42 58 0x0000.00E8 Ethernet Controller 44 60 0x0000.00F0 USB 45 61 – Reserved 46 62 0x0000.00F8 ?DMA Software 47 63 0x0000.00FC ?DMA Error 48–52 64–68 – Reserved 53 69 0x0000.0114 EPI 54 70 0x0000.0118 GPIO Port J 55–56 71–72 – Reserved 57 73 0x0000.0124 SSI 2 58 74 0x0000.01f20;BACKGROUND-COLOR:#4ae2f7">28 SSI 3 59 75 0x0000.012C UART3 60 76 0x0000.0130 UART4 61–63 77–79 – Reserved 64 80 0x0000.0140 CAN0 INT0 65 81 0x0000.0144 CAN0 INT1 66 82 0x0000.0148 CAN1 INT0 67 83 0x0000.014C CAN1 INT1 68–71 84–87 – Reserved 72 88 0x0000.0160 ADCINT1 73 89 0x0000.0164 ADCINT2 74 90 0x0000.0168 ADCINT3 75 91 0x0000.016C ADCINT4 76 92 0x0000.0170 ADCINT5 77 93 0x0000.0174 ADCINT6 78 94 0x0000.0178 ADCINT7 79 95 0x0000.017C ADCINT8 80 96 0x0000.0180 CTOMIPC1 81 97 0x0000.0184 CTOMIPC2 82 98 0x0000.0188 CTOMIPC3 83 99 0x0000.018C CTOMIPC4 84–87 100–103 – Reserved 88 104 0x0000.01A0 RAM Single Error 89 105 0x0000.01A4 System / USB PLL Out of Lock 90 106 0x0000.01A8 M3 Flash Single Error 91 107 0x0000.01AC PBIST Done 92–133 108–149 – Reserved 24 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-16. Exceptions from Cortex-M3 Core to NVIC Vector Address or Exception Type Priority(1) Vector Number Activation Offset(2) Stack top is loaded from – – 0 0x0000.0000 the first entry of the vector table on reset. Reset –3 (highest) 1 0x0000.0004 Asynchronous Asynchronous On Concerto devices activated by clock fail Non-Maskable Interrupt –2 2 0x0000.0008 condition, Cf20;BACKGROUND-COLOR:#4ae2f7">28 PIE error, (NMI) external M3GPIO NMI input signal, and Cf20;BACKGROUND-COLOR:#4ae2f7">28 NMI WD timeout reset. Hard Fault –1 3 0x0000.000C – Memory Management programmable(3) 4 0x0000.0010 Synchronous Synchronous when precise and asynchronous when imprecise. On Concerto devices Bus Fault programmable(3) 5 0x0000.0014 activated by memory access errors and RAM and flash uncorrectable data errors. Usage Fault programmable(3) 6 0x0000.0018 Synchronous – – 7–10 – Reserved SVCall programmable(3) 11 0x0000.002C Synchronous Debug Monitor programmable(3) 12 0x0000.0030 Synchronous – – 13 – Reserved PendSV programmable(3) 14 0x0000.0038 Asynchronous SysTick programmable(3) 15 0x0000.003C Asynchronous Interrupts programmable (4) 16 and above 0x0000.0040 and above Asynchronous (1) 0 is the default priority for all the programmable priorities (2) See the "Vector Table" subsection of the "Exception Model" section in the Cortex-M3 Processor chapter of the Concerto Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Technical Reference Manual (literature number SPRUH22). (3) See SYSPRI1 in the Cortex-M3 Peripherals chapter of the Concerto Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Technical Reference Manual (literature number SPRUH22). (4) See PRIn registers in the Cortex-M3 Peripherals chapter of the Concerto Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Technical Reference Manual (literature number SPRUH22). 3.3.5 Cortex-M3 Vector Table Each peripheral interrupt of Table 3-15 is assigned an address offset containing the location of the peripheral interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers 16–107). Similarly, each exception interrupt of Table 3-16 (including Reset) is also assigned an address offset containing the location of the exception interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers 1–15). In addition to interrupt vectors, the vector table also contains the initial stack pointer value at table location 0. Following system reset, the vector table base is fixed at address 0x0000.0000. Privileged software can write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000 0200 to 0x3FFF FE00. Note that when configuring the VTABLE register, the offset must be aligned on a 512-byte boundary. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 25 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.3.6 Cortex-M3 Local Peripherals The Cortex-M3 local peripherals include two Watchdogs, an NMI Watchdog, four General-Purpose Timers, four SSI peripherals, two CAN peripherals, five UARTs, two I2 C peripherals, Ethernet, USB + PHY, EPI, and ?CRC (Cyclic Redundancy Check). The USB and EPI are accessible through the AHB Bus (Advanced High-Performance Bus). The EPI peripheral is also accessible from the Control Subsystem. The remaining peripherals are accessible through the APB Bus (Advanced Peripheral Bus). The APB and AHB bus cycles originate from the CPU System Bus or the ?DMA Bus via a bus bridge. While the Cortex-M3 CPU has access to all the peripherals, the ?DMA has access to most, with the exception of the ?CRC, Watchdogs, NMI Watchdog, CAN peripherals, and the I2 C peripheral. The Cortex- M3 peripherals connect to the Concerto device pins via GPIO_MUX1. Most of the peripherals also generate event signals for the ?DMA and the NVIC. The Watchdogs receive M3SWRST from the NVIC (triggered by software) and send M3WDRST[1:0] reset requests to the Reset block. The NMI Watchdog receives the M3NMI event from the NMI block and sends the M3NMIRST request to the Resets block. See Section 7.2 for more information on the Cortex-M3 peripherals. 3.3.7 Cortex-M3 Local Memory The Local Memory includes Boot ROM; Secure Flash with ECC; Secure C0/C1 RAM with ECC; and C2/C3 RAM with Parity Error Checking. The Boot ROM and Flash are both accessible through the I- CODE and D-CODE Buses. Flash registers can also be accessed by the Cortex-M3 CPU through the APB Bus. All Local Memory is accessible from the Cortex-M3 CPU; the C2/C3 RAM is also accessible by the ?DMA. Two types of error correction events can be generated during access of the Local Memory: uncorrectable errors and single errors. The uncorrectable errors (including one from the Shared Memories) generate a Bus Fault Exception to the Cortex-M3 CPU. The less critical single errors go to the NVIC where they can result in maskable interrupts to the Cortex-M3 CPU. 3.3.8 Cortex-M3 Accessing Shared Resources and Analog Peripherals There are several memories, digital peripherals, and analog peripherals that can be accessed by both the Master and Control Subsystems. They are grouped into Shared Resources and the Analog Subsystem. The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and eight individually configurable Shared RAM blocks. The RAMs of the Shared Resources block have Parity Error Checking. The Message RAMs and the Shared RAMs can be accessed by the Cortex-M3 CPU and ?DMA. The MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem, having R/W access for the Cortex-M3/?DMA and read-only access for the Cf20;BACKGROUND-COLOR:#4ae2f7">28x/DMA. The CTOM Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having R/W access for the Cf20;BACKGROUND-COLOR:#4ae2f7">28x/DMA and read-only access for the Cortex-M3/?DMA. The IPC registers provide up to 32 handshaking channels to coordinate the transfer of data through the Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays associated with polling). The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way; however, the direction of the data flow can be individually set for each block to be from Master to Control Subsystem or from Control to Master Subsystem. The Analog Subsystem has ADC1, ADC2, and Analog Comparator peripherals that can be accessed through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU only. The Cortex-M3 CPU accesses the ACIB through the System Bus, and the ?DMA through the ?DMA Bus. The ACIB arbitrates for access to the ADC and Analog Comparator registers between 26 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 CPU/DMA bus cycles of the Master Subsystem with those of the Control Subsystem. In addition to managing bus cycles, the ACIB also transfers End-of-Conversion ADC interrupts to the Master Subsystem (as well as to the Control Subsystem). The eight EOC sources from ADC1 and the eight EOC sources from ADC2 are AND-ed together by the ACIB, with the resulting eight ADC interrupts going to destinations in both the Master Subsystem and the Control Subsystem. See Section 7.1 for more information on shared resources and analog peripherals. 3.4 Control Subsystem The Control Subsystem includes the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU/FPU/VCU, Peripheral Interrupt Expansion (PIE) block, DMA, Cf20;BACKGROUND-COLOR:#4ae2f7">28x Peripherals, and Local Memory. Additionally, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU and DMA have access to Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and to Analog Peripherals via the Analog Common Interface Bus. Figure 3-2 shows the Control Subsystem. 3.4.1 Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU/FPU/VCU The Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Concerto MCU family is a member of the TMS320C2000 MCU platform. The Concerto Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU/FPU has the same 32-bit fixed-point architecture as TI's existing Piccolo MCUs, combined with a single-precision (32-bit) IEEE 754 FPU of TI's existing Delfino MCUs. Each Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x device is a very efficient C/C++ engine, enabling users to develop their system control software in a high-level language. Each Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x device also enables math algorithms to be developed using C/C++. The device is equally efficient at DSP math tasks and at system control tasks. The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. With the addition of the fast interrupt response with automatic context save of critical registers, the device is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the device to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special conditional store operations further improve performance. The VCU extends the capabilities of the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU and Cf20;BACKGROUND-COLOR:#4ae2f7">28x+FPU processors by adding additional instructions to accelerate Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms. No changes have been made to existing instructions, pipeline, or memory bus architecture. Therefore, programs written for the Cf20;BACKGROUND-COLOR:#4ae2f7">28x are completely compatible with the Cf20;BACKGROUND-COLOR:#4ae2f7">28x+VCU. There are two events generated by the FPU block that go to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x PIE: LVF and LUV. Inside PIE, these and other events from Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals and memories result in 12 PIE interrupts PIEINTS[12:1] into the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU. The Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU also receives three additional interrupts directly (instead of through PIE) from Timer 1 (TINT1), from Timer 2 (TINT2), and from the NMI block (Cf20;BACKGROUND-COLOR:#4ae2f7">28uNMIINT). The Cf20;BACKGROUND-COLOR:#4ae2f7">28x has two low-power modes: IDLE and STANDBY. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 27 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 3-2. Control Subsystem f20;BACKGROUND-COLOR:#4ae2f7">28 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.4.2 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Core Hardware Built-In Self-Test The Concerto microcontroller Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU core includes a HWBIST controller for testing the CPU core logic for errors. Tests are initiated by software whenever convenient (at start-up, idle, and so on), which allows for periodic logic tests to ensure that the CPU core logic is working correctly. During a test cycle, all interrupts are logged by the HWBIST controller and re-issued after the test cycle completes to ensure that no interrupts are missed. In the event of a logic error, the HWBIST controller generates an NMI on both cores to signal that an error has been detected. This action allows for the software to gracefully handle any detected logic errors. 3.4.3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Peripheral Interrupt Expansion The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x, 66 of the possible 96 interrupts are used. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of 12 interrupt lines supports up to 8 simultaneously active interrupts. Each of the 96 interrupts has its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence, the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled or disabled within the PIE block. See Table 3-17 for PIE interrupt assignments. Table 3-17. PIE Peripheral Interrupts(1) PIE INTERRUPTS CPU INTERRUPTS INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 Cf20;BACKGROUND-COLOR:#4ae2f7">28.LPMWAKE TINT0 Reserved XINT2 XINT1 Reserved ADCINT2 ADCINT1 INT1 (Cf20;BACKGROUND-COLOR:#4ae2f7">28LPM) (TIMER 0)ADC) (ADC) 0x0D4E 0x0D4C 0x0D4A 0x0D48 0x0D46 0x0D44 0x0D42 0x0D40 EPWM8_TZINT EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT INT2 (ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0x0D5E 0x0D5C 0x0D5A 0x0D58 0x0D56 0x0D54 0x0D52 0x0D50 EPWM8_INT EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT INT3 (ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0x0D6E 0x0D6C 0x0D6A 0x0D68 0x0D66 0x0D64 0x0D62 0x0D60 EPWM9_TZINT Reserved ECAP6_INT ECAP5_INT ECAP4_INT ECAP3_INT ECAP2_INT ECAP1_INT INT4 (ePWM9) – (eCAP6) (eCAP5) (eCAP4) (eCAP3) (eCAP2) (eCAP1) 0x0D7E 0x0D7C 0x0D7A 0x0D78 0x0D76 0x0D74 0x0D72 0x0D70 EPWM9_INT Reserved Reserved Reserved Reserved EQEP3_INT EQEP2_INT EQEP1_INT INT5 (ePWM9)eQEP3) (eQEP2) (eQEP1) 0x0D8E 0x0D8C 0x0D8A 0x0D88 0x0D86 0x0D84 0x0D82 0x0D80 Reserved Reserved MXINTA MRINTA Reserved Reserved SPITXINTA SPIRXINTA INT6 – – (McBSPA) (McBSPA) – – (SPIA) (SPIA) 0x0D9E 0x0D9C 0x0D9A 0x0D98 0x0D96 0x0D94 0x0D92 0x0D90 Reserved Reserved DINTCH6 DINTCH5 DINTCH4 DINTCH3 DINTCH2 DINTCH1 INT7 – – (Cf20;BACKGROUND-COLOR:#4ae2f7">28 DMA) (Cf20;BACKGROUND-COLOR:#4ae2f7">28 DMA) (Cf20;BACKGROUND-COLOR:#4ae2f7">28 DMA) (Cf20;BACKGROUND-COLOR:#4ae2f7">28 DMA) (Cf20;BACKGROUND-COLOR:#4ae2f7">28 DMA) (Cf20;BACKGROUND-COLOR:#4ae2f7">28 DMA) 0x0DAE 0x0DAC 0x0DAA 0x0DA8 0x0DA6 0x0DA4 0x0DA2 0x0DA0 Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A INT8 I2CA) (I2CA) 0x0DBE 0x0DBC 0x0DBA 0x0DB8 0x0DB6 0x0DB4 0x0DB2 0x0DB0 Reserved Reserved Reserved Reserved Reserved Reserved SCITXINTA SCIRXINTA INT9 SCIA) (SCIA) 0x0DCE 0x0DCC 0x0DCA 0x0DC8 0x0DC6 0x0DC4 0x0DC2 0x0DC0 ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1 INT10 (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) 0x0DDE 0x0DDC 0x0DDA 0x0DD8 0x0DD6 0x0DD4 0x0DD2 0x0DD0 Reserved Reserved Reserved Reserved MTOCIPCINT4 MTOCIPCINT3 MTOCIPCINT2 MTOCIPCINT1 INT11 IPC) (IPC) (IPC) (IPC) 0x0DEE 0x0DEC 0x0DEA 0x0DE8 0x0DE6 0x0DE4 0x0DE2 0x0DE0 LUF LVF EPI_INT Cf20;BACKGROUND-COLOR:#4ae2f7">28RAMACCVIOL Cf20;BACKGROUND-COLOR:#4ae2f7">28RAMSINGERR Reserved Cf20;BACKGROUND-COLOR:#4ae2f7">28FLSINGERR XINT3 INT12 (Cf20;BACKGROUND-COLOR:#4ae2f7">28FPU) (Cf20;BACKGROUND-COLOR:#4ae2f7">28FPU) (EPI) (Memory) (Memory) – (Memory) (Ext. Int. 3) 0x0DFE 0x0DFC 0x0DFA 0x0DF8 0x0DF6 0x0DF4 0x0DF2 0x0DF0 (1) Out of the 96 possible interrupts, 66 interrupts are currently used. The remaining interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts: 1) No peripheral within the group is asserting interrupts. 2) No peripheral interrupts are assigned to the group (example PIE group 11). Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 29 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.4.4 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Direct Memory Access The Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA module provides a hardware method of transferring data between peripherals, between memory, and between peripherals and memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as the data is transferred as well as "ping-pong" data between buffers. These features are useful for structuring data into blocks for optimal CPU processing. The interrupt trigger source for each of the six DMA channels can be configured separately and each channel contains its own independent PIE interrupt to notify the CPU when a DMA transfer has either started or completed. Five of the six channels are exactly the same, while Channel 1 has one additional feature: the ability to be configured at a higher priority than the others. 3.4.5 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Local Peripherals The Cf20;BACKGROUND-COLOR:#4ae2f7">28x local peripherals include an NMI Watchdog, three Timers, four Serial Port Peripherals (SCI, SPI, McBSP, I2 C), an EPI, and three types of Control Peripherals (ePWM, eQEP, eCAP). All peripherals are accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU via the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Memory Bus. Additionally, the McBSP and ePWM are accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA Bus. The EPI peripheral is also accessible from the Master Subsystem. The Serial Port Peripherals and the Control Peripherals connect to Concerto's pins via the GPIO_MUX1 block. Internally, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals generate events to the PIE block, Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA, and the Analog Subsystem. The Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI Watchdog receives a Cf20;BACKGROUND-COLOR:#4ae2f7">28NMI event from the NMI block and sends a counter timeout event to the Cortex-M3 NMI block and the Resets block to flag a potentially critical condition. The ePWM peripheral receives events that can be used to trip the ePWM outputs EPWMxA and EPWMxB. These events include ECCDBLERR event from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Local Memory, PIENMIERR and EMUSTOP events from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU, and up to 12 trips from GPIO_MUX1. See Section 7.3 for more information on Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals. 3.4.6 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Local Memory The Cf20;BACKGROUND-COLOR:#4ae2f7">28x Local Memory includes Boot ROM; Secure Flash with ECC; Secure L0/L1 RAM with ECC; L2/L3 RAM with Parity Error Checking; and M0/M1 with ECC. All local memories are accessible from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU; the L2/L3 RAM is also accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA. Two types of error correction events can be generated during access of the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Local Memory: uncorrectable errors and single errors. The uncorrectable errors propagate to the NMI block where they can become the Cf20;BACKGROUND-COLOR:#4ae2f7">28NMI to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI Watchdog and the Cf20;BACKGROUND-COLOR:#4ae2f7">28NMIINT non-maskable interrupt to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU. The less critical single errors go to the PIE block where they can become maskable interrupts to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU. 3.4.7 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Accessing Shared Resources and Analog Peripherals There are several memories, digital peripherals, and analog peripherals that can be accessed by both the Master and Control Subsystems. They are grouped into the Shared Resources and the Analog Subsystem. The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and eight individually configurable Shared RAM blocks. The Message RAMs and the Shared RAMs can be accessed by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU and DMA and have Parity- Error Checking. The MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem, having R/W access for the Cortex-M3/?DMA and read-only access for the Cf20;BACKGROUND-COLOR:#4ae2f7">28x/DMA. The CTOM Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having R/W access for the Cf20;BACKGROUND-COLOR:#4ae2f7">28x/DMA and read-only access for the Cortex-M3/?DMA. The IPC registers provide up to 32 handshaking channels to coordinate transfer of data through the Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays associated with polling). 30 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way; however, the direction of the data flow can be individually set for each block to be from Master to Control Subsystem or from Control to Master Subsystem. See Section 7.1 for more information on shared resources and analog peripherals. 3.5 Analog Subsystem The Analog Subsystem has ADC1, ADC2, and six Analog Comparator + DAC units that can be accessed via the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU only. The Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU accesses the ACIB through the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Memory Bus, and the Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA through the Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA Bus. The ACIB arbitrates for access to ADC and Analog Comparator registers between CPU/DMA bus cycles of the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Subsystem with those of the Cortex-M3 Subsystem. In addition to managing bus cycles, the ACIB also transfers Start-Of-Conversion triggers to the Analog Subsystem and returns End-Of-Conversion ADC interrupts to both the Master Subsystem and the Control Subsystem. There are 22 possible Start-Of-Conversion (SOC) sources from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Subsystem that are mapped to a total of 8 possible SOC triggers inside the Analog Subsystem (to ADC1 and ADC2). Going the other way, eight End-Of-Conversion (EOC) sources from ADC1 and eight EOC sources from ADC2 are AND-ed together to form eight interrupts going to destinations in both the Master and Control Subsystems. Inside the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Subsystem, all eight EOC interrupts go to the PIE, but only four of the same eight go to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA. The Concerto MCU Analog Subsystem has two independent Analog-to-Digital Converters (ADC1, ADC2); six Analog Comparators + DAC units; and an ACIB to facilitate analog data communications with Concerto's two digital subsystems (Cortex-M3 and Cf20;BACKGROUND-COLOR:#4ae2f7">28x). Figure 3-3 shows the Analog Subsystem. 3.5.1 ADC1 The ADC1 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which 10 are currently pinned out. The analog channels are internally pre-assigned to two Sample-and-Hold (S/H) units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in ADC1 result registers. The two S/H units enable simultaneous sampling of two analog signals at a time. Additional channels or channel pairs are converted sequentially. SOC triggers from the Control Subsystem initiate analog-to-digital conversions. EOC interrupts from ADCs notify the Master and Control Subsystems that the conversion results are ready to be read from ADC1 result registers. See Section 7.1.1 for more information on ADC peripherals. 3.5.2 ADC2 The ADC2 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which 10 are currently pinned out. The analog channels are internally preassigned to two S/H units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in the ADC2 result registers. The two S/H units enable simultaneous sampling of two analog signals at a time. Additional channels or channel pairs are converted sequentially. SOC triggers from the Control Subsystem initiate analog-to-digital conversions. EOC interrupts from ADCs notify the Master and Control Subsystems that the conversion results are ready to be read from ADC2 result registers. See Section 7.1.1 for more information on ADC peripherals. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 31 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 3-3. Analog Subsystem 32 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.5.3 Analog Comparator + DAC There are six Comparator blocks enabling simultaneous comparison of multiple pairs of analog inputs, resulting in six digital comparison outputs. The external analog inputs that are being compared in the comparators come from AIO_MUX1 and AIO_MUX2 blocks. These analog inputs can be compared against each other or the outputs of 10-bit DACs (Digital-to-Analog Converters) inside individual Comparator modules. The six comparator outputs go to the GPIO_MUX2 block where they can be mapped to six out of eight available pins. Note that in order to use these comparator outputs to trip the Cf20;BACKGROUND-COLOR:#4ae2f7">28x EPWMA/B outputs, they must be first routed externally from pins of the GPIO_MUX2 block to selected pins of the GPIO_MUX1 block before they can be assigned to selected 12 ePWM Trip Inputs. See Section 7.1.2 for more information on the analog comparator + DAC. 3.5.4 Analog Common Interface Bus The ACIB links the Master and Control Subsystems with the Analog Subsystem. The ACIB enables the Cortex-M3 CPU/?DMA and Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU/DMA to access Analog Subsystem registers, to send SOC Triggers to the Analog Subsystem, and to receive EOC Interrupts from the Analog Subsystem. The Cortex-M3 uses its System Bus and the ?DMA Bus to read from ADC Result registers. The Cf20;BACKGROUND-COLOR:#4ae2f7">28x uses its Memory Bus and the DMA bus to access ADC Result registers and other registers of the Analog Subsystem. The ACIB arbitrates between up to four possibly simultaneously occurring bus cycles on the Master/Control Subsystem side of ACIB to access the ADC and Analog Comparator registers on the Analog Subsystem side. Additionally, ACIB maps up to 22 SOC trigger sources from the Control Subsystem to 8 SOC trigger destinations inside the Analog Subsystem (shared between ADC1 and ADC2), and up to 16 ADC EOC interrupt sources from the Analog Subsystem to 8 destinations inside the Master and Control Subsystems. The eight ADC interrupts are the result of AND-ing of eight EOC interrupts from ADC1 with 8 EOC interrupts from ADC2. The total of 16 possible ADC1 and ADC2 interrupts are sharing the 8 interrupt lines because it is unlikely that any application would need all 16 interrupts at the same time. Eight registers (TRIG1SEL–TRIG8SEL) configure eight corresponding SOC triggers to assign 1 of 22 possible trigger sources to each SOC trigger. There are two registers that provide status of ACIB to the Master Subsystem and to the Control Subsystem. The Cortex-M3 can read the MCIBSTATUS register to verify that the Analog Subsystem is properly powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are correctly propagating between the Master, Control, and Analog subsystems. The Cf20;BACKGROUND-COLOR:#4ae2f7">28x can read the CCIBSTATUS register to verify that the Analog Subsystem is properly powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are correctly propagating between the Master, Control, and Analog subsystems. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 33 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.6 Master Subsystem NMIs The Cortex-M3 NMI Block generates an M3NMIINT non-maskable interrupt to the Cortex-M3 CPU and an M3NMI event to the NMI Watchdog in response to potentially critical conditions existing inside or outside the Concerto MCU. When able to respond to the M3NMIINT interrupt, the Cortex-M3 CPU may address the NMI condition and disable the NMI Watchdog. Otherwise, the NMI Watchdog counts out and an M3NMIRST reset signal is sent to the Resets block. The inputs to the Cortex-M3 NMI block include the Cf20;BACKGROUND-COLOR:#4ae2f7">28NMIRST, PIENMIERR, CLOCKFAIL, ACIBERR, EXTGPIO, MLBISTERR, and CLBISTERR signals. The Cf20;BACKGROUND-COLOR:#4ae2f7">28NMIRST comes from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI Watchdog; Cf20;BACKGROUND-COLOR:#4ae2f7">28NMIRST indicates that the Cf20;BACKGROUND-COLOR:#4ae2f7">28x was not able to prevent the Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI Watchdog counter from counting out. PIENMIERR indicates that an error condition was generated during the NMI vector fetch from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x PIE block. The CLOCKFAIL input comes from the Master Clocks Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog Common Interface Bus. EXTGPIO comes from the GPIO_MUX1 to announce an external emergency. MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature mismatch error has been detected. CLBISTERR is generated by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x core to signal that a BIST time-out or signature mismatch error has been detected. The Cortex-M3 NMI block can be accessed via the Cortex-M3 NMI configuration registers—including the MNMIFLG, MNMIFLGCLR, and MNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags, and force the flags to active state, respectively. Figure 3-4 shows the Cortex-M3 NMI and Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI. 3.7 Control Subsystem NMIs The Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI Block generates a Cf20;BACKGROUND-COLOR:#4ae2f7">28NMIINT non-maskable interrupt to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU and a Cf20;BACKGROUND-COLOR:#4ae2f7">28NMI event to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI Watchdog in response to potentially critical conditions existing inside the Concerto MCU. When able to respond to the Cf20;BACKGROUND-COLOR:#4ae2f7">28NMIINT interrupt, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU may address the NMI condition and disable the Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI Watchdog. Otherwise, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI Watchdog counts out and the Cf20;BACKGROUND-COLOR:#4ae2f7">28NMIRST reset signal is sent to the Resets block and the Cortex-M3 NMI Block, where the Cortex-M3 NMI Block can generate an NMI to the Cortex-M3 processor. The inputs to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI block include the CLOCKFAIL, ACIBERR, RAMUNCERR, FLASHUNCERR, PIENMIERR, CLBISTERR, and MLBISTERR signals. The CLOCKFAIL input comes from the Clocks Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog Common Interface Bus. The RAMUCERR and FLASHUNCERR announce the occurrence of uncorrectable error conditions during access to the Flash or RAM (local or shared). PIENMIERR indicates that an error condition was generated during NMI vector fetch from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x PIE block. MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature mismatch error has been detected. CLBISTERR is generated by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x core to signal that a BIST time- out or signature mismatch error has been detected. The Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI block can be accessed via the Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI configuration registers—including the CNMIFLG, CNMIFLGCLR, and CNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags, and force the flags to active state, respectively. Figure 3-4 shows the Cortex-M3 NMI and Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI. 34 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 3-4. Cortex-M3 NMI and Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 35 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.8 Resets The Concerto MCU has two external reset pins: XRS for the Master and Control Subsystems and ARS for the Analog Subsystem. TI recommends that these two pins be externally tied together with a board signal trace. The XRS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset signal out from inside of the chip. A reset pulse driven into the XRS pin resets the Master and Control Subsystems. A reset pulse can also be driven out of the XRS pin by the Power-On Reset (POR) block of the Master and Control Subsystems (see Section 3.9). A reset pulse can be driven out of the XRS pin when the two Cortex-M3 Watchdogs or the Cortex-M3 NMI Watchdog time out. There are some requirements on the XRS pin: 1. During power up, the XRS pin must be held low for at least eight X1 cycles after the input clock is stable. This requirement is to enable the entire device to start from a known condition. 2. TI recommends that no voltage larger than 0.7 V be applied to any pin prior to powering up the device. Voltages applied to pins on an unpowered device can lead to unpredictable results. The ARS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset signal out from inside of the chip. A reset pulse driven into the ARS pin resets the Analog Subsystem. A reset pulse can be driven out of the ARS pin by the POR block of the Analog Subsystem. Figure 3-5 shows the resets. 3.8.1 Cortex-M3 Resets The Cortex-M3 CPU and NVIC (Nested Vectored Interrupt Controller) are both reset by the POR or the M3SYSRST reset signal. In both cases, the Cortex-M3 CPU restarts program execution from the address provided by the reset entry in the vector table. A register can later be referenced to determine the source of the reset. The M3SYSRST signal also propagates to the Cortex-M3 peripherals and the rest of the Cortex-M3 Subsystem. The M3SYSRST has four possible sources: XRS, M3WDOGS, M3SWRST, and M3DBGRST. The M3WDOGS is set in response to time-out conditions of the two Cortex-M3 Watchdogs or the Cortex-M3 NMI Watchdog. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. In addition to driving M3SYSRST, these two resets also propagate to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Subsystem and the Analog Subsystem. The M3RSNIN bit can be set inside the CRESCNF register to selectively reset the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Subsystem from the Cortex-M3, and ACIBRST bit of the same register selectively resets the Analog Common Interface Bus. In addition to driving reset signals to other parts of the chip, the Cortex-M3 can also detect a Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSRST reset being set inside the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Subsystem by reading the CRES bit of the CRESSTS register. Cortex-M3 software can also set bits in the SRCR register to selectively reset individual Cortex-M3 peripherals, provided they are enabled inside the DC (Device Configuration) register. The Reset Cause register (MRESC) can be read to find out if the latest reset was caused by External Reset, POR, Watchdog Timer 0, Watchdog Timer 1, or Software Reset from NVIC. 36 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 3-5. Resets Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 37 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.8.2 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Resets The Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU is reset by the Cf20;BACKGROUND-COLOR:#4ae2f7">28RSTIN signal, and the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU in turn resets the rest of the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Subsystem with the Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSRST signal. When reset, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x restarts program execution from the address provided at the top of the Boot ROM Vector Table. The Cf20;BACKGROUND-COLOR:#4ae2f7">28RSTIN has five possible sources: XRS, Cf20;BACKGROUND-COLOR:#4ae2f7">28NMIWD, M3SWRST, M3DBGRST, and the M3RSNIN. The Cf20;BACKGROUND-COLOR:#4ae2f7">28NMIWD is set in response to time-out conditions of the Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI Watchdog. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor in order to propagate to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Subsystem. M3RSNIN reset comes from the Cortex-M3 Subsystem to selectively reset the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Subsystem from Cortex-M3 software. The Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor can learn the status of the internal ACIBRST reset signal and the external XRS pin by reading the DEVICECNF register. 3.8.3 Analog Subsystem and Shared Resources Resets Both the Analog Subsystem and the resources shared between the Cf20;BACKGROUND-COLOR:#4ae2f7">28x and Cortex-M3 subsystems (IPC, MSG RAM, Shared RAM) are reset by the SRXRST reset signal. Additionally, the Analog Subsystem is also reset by the internal ACIBRST signal from the Cortex-M3 Subsystem and the external ARS pin, (should be externally tied to the XRS pin), which can be reset by the POR circuitry. The SRXRST has three possible sources: XRS, M3SWRST, and M3DBGRST. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor in order to propagate to the Analog Subsystem and the Shared Resources. Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore, EPI is reset by M3SYSRST. 3.8.4 Device Boot Sequence Concerto's boot sequence is used to configure the Master Subsystem and the Control Subsystem for execution of application code. The boot sequence involves both internal resources, and resources external to the device. These resources include: Master Subsystem Bootloader code (M-Bootloader) factory- programmed inside the Master Subsystem Boot ROM (M-Boot ROM); Control Subsystem Bootloader code (C-Bootloader) factory-programmed inside the Control Subsystem Boot ROM (C-Boot ROM); four GPIO_MUX pins for Master boot mode selection; internal Flash and RAM memories; and selected Cortex- M3 and Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals for loading the application code into the Master and Control Subsystems. The boot sequence starts when the Master Subsystem comes out of reset, which can be caused by device power up, external reset, debugger reset, software reset, Cortex-M3 watchdog reset, or Cortex-M3 NMI watchdog reset. While the M-Bootloader starts executing first, the C-Bootloader starts soon after, and then both bootloaders work in tandem to configure the device, load application code for both processors (if not already in the Flash), and branch the execution of each processor to a selected location in the application code. Execution of the M-Bootloader commences when an internal reset signal goes from active to inactive state. At that time, the Control Subsystem and the Analog Subsystem continue to be in reset state until the Master Subsystem takes them out of reset. The M-Bootloader first initializes some device-level functions, then the M-Bootloader initializes the Master Subsystem. Next, the M-Bootloader takes the Control Subsystem and the Analog Subsystem/ACIB out of reset. When the Control Subsystem comes out of reset, its own C-Bootloader starts executing in parallel with the M-Bootloader. After initializing the Control Subsystem, the C-Bootloader enters the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor into the IDLE mode (to wait for the M- Bootloader to wake up the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor later via the MTOCIPC1 interrupt). Next, the M-Bootloader reads four GPIO pins (see Table 3-18) to determine the boot mode for the rest of the M-Bootloader operation. 38 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-18. Master Subsystem Boot Mode Selection(1) Boot PF2_GPIO34 PF3_GPIO35 PG7_GPIO47 PG3_GPIO43 Master Subsystem Boot Modes Mode No. (BOOT_3)(2) (3) (BOOT_2)(2) (BOOT_1)(2) (BOOT_0)(2) 0 Boot from Parallel GPIO 0 0 0 0 1 Boot to Master Subsystem RAM 0 0 0 1 Boot from Master Subsystem serial peripherals 2 0 0 1 0 (UART0/SSI0/I2C0) 3 Boot from Master Subsystem CAN interface 0 0 1 1 4 Boot from Master Subsystem Ethernet interface 0 1 0 0 5 Not supported (Defaults to Boot-to-Flash) 0 1 0 1 6(5) Boot-to-OTP 0 1 1 0 7 Boot to Master Subsystem Flash memory 0 1 1 1 8(4) Not supported (Defaults to Boot-to-Flash) 1 0 0 0 Boot from Master Subsystem serial peripheral – 9(4) 1 0 0 1 SSI0 Master Boot from Master Subsystem serial peripheral – 10(4) 1 0 1 0 I2C0 Master 11(4) Not supported (Defaults to Boot-to-Flash) 1 0 1 1 12(4) Not supported (Defaults to Boot-to-Flash) 1 1 0 0 13(4) Not supported (Defaults to Boot-to-Flash) 1 1 0 1 14(4) Not supported (Defaults to Boot-to-Flash) 1 1 1 0 15(4) Not supported (Defaults to Boot-to-Flash) 1 1 1 1 (1) Silicon revision A allows the user to change the GPIO pins used to determine the boot mode. Silicon revision 0 does not have this option. See the Concerto Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Technical Reference Manual (literature number SPRUH22) for additional information. (2) By default, GPIO terminals are not pulled up (they are floating). (3) On silicon revision 0, PF2_GPIO34 is a "don't care". So, the state of PF2_GPIO34 should not affect boot mode selection. (4) Boot Modes 8–15 are not supported on silicon revision 0. (5) Supported only in TMS version. On all other versions, this mode defaults to Boot-to-Flash. Boot Mode 7 and Boot Mode 15 cause the Master program to branch execution to the application in the Master Flash memory. This branching requires that the Master Flash be already programmed with valid code; otherwise, a hard fault exception is generated and the Cortex-M3 goes back to the above reset sequence. (Therefore, for a factory-fresh device, the M-Bootloader will be in a continuous reset loop until the emulator is connected and a debug session started.) If the Master Subsystem Flash has already been programmed, the application code will start execution. Typically, the Master Subsystem application code will then establish data communication with the Cf20;BACKGROUND-COLOR:#4ae2f7">28x [through the IPC (Interprocessor Communications peripheral)] to coordinate the rest of the boot process with the Control Subsystem. Note that following reset, the internal pullup resistors on GPIOs are disabled. Therefore, Boot Mode 15, for example, will typically require four external pullups. Boot Mode 1 causes the Master boot program to branch to Cortex-M3 RAM, where the Cortex-M3 processor starts executing code that has been preloaded earlier. Typically, this mode is used during development of application code meant for Flash, but which has to be first tested running out of RAM. In this case, the user would typically load the application code into RAM using the debugger, and then issue a debugger reset, while setting the four boot pins to 0001b. From that point on, the rest of the boot process on the Master Subsystem side is controlled by the application code. Boot Modes 0, 2, 3, 4, 9, 10, and 12 are used to load the Master application code from an external peripheral before branching to the application code. This process is different from the process in Boot Modes 1, 7, and 15, where the application code was either already programmed in Flash or loaded into RAM by the emulator. If the boot mode selection pins are set to 0000b, the M-Bootloader (running out of M-Boot ROM) will start uploading the Master application code from preselected Parallel GPIO_MUX pins. If the boot pins are set to 0010b, the application code will be loaded from the Master Subsystem UART0, SSI0, or I2C0 peripheral. (SSI0 and I2C0 are configured to work in Slave mode in this Boot Mode.) If the Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 39 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn boot pins are set to 0011b, the application code will be loaded from the Master Subsystem CAN interface. Furthermore, if the boot pins are set to 0100b, the application code will be loaded through the Master Subsystem Ethernet interface; the IOs used in this Boot Mode are compatible with the Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x device. If the boot pins are set to 1001b or 1010b, then the application code will be loaded through the SSI0 or I2C0 interface, respectively. SSI0 and I2C0 loaders work in Master Mode in this boot mode. Regardless of the type of boot mode selected, once the Master application code is resident in Master Flash or RAM, the next step for the M-Bootloader is to branch to Master Flash or RAM. At that point, the application code takes over control from the M-Bootloader, and the boot process continues as prescribed by the application code. At this stage, the Master application program typically establishes communication with the C-Bootloader, which by now, would have already initialized the Control Subsystem and forced the Cf20;BACKGROUND-COLOR:#4ae2f7">28x to go into IDLE mode. To wake the Control Subsystem out of IDLE mode, the Master application issues the Master-to-Control-IPC-interrupt 1 (MTOCIPCINT1). Once the data communication has been established through the IPC, the boot process can now also continue on the Control Subsystem side. The rest of the Control Subsystem boot process is controlled by the Master Subsystem application issuing IPC instructions to the Control Subsystem, with the C-Bootloader interpreting the IPC commands and acting on them to continue the boot process. At this stage, a boot mode for the Control Subsystem can be established. The Control Subsystem boot modes are similar to the Master Subsystem boot modes, except for the mechanism by which they are selected. The Control Subsystem boot modes are chosen through the IPC commands from the Master application code to the C-Bootloader, which interprets them and acts accordingly. The choices are, as above, to branch to already existing Control application code in Flash, to branch to preloaded code in RAM (development mode), or to upload the Control application code from one of several available peripherals (see Table 3-19). As before, once the Control application code is in place (in Flash or RAM), the C-Bootloader branches to Flash or RAM, and from that point on, the application code takes over. Table 3-19. Control Subsystem Boot Mode Selection Control Subsystem MTOCIPCBOOTMODE Description Boot Modes Register Value Upon receiving this command from the Master Subsystem, C-Boot BOOT_FROM_RAM 0x0000 0001 ROM will branch to the Control Subsystem RAM entry point location and start executing code from there. Upon receiving this command, C-Boot ROM will branch to the BOOT_FROM_FLASH 0x0000 0002 Control Subsystem FLASH entry point and start executing code from there. Upon receiving this command, C-Boot ROM will boot from the BOOT_FROM_SCI 0x0000 0003 Control Subsystem SCI peripheral. Upon receiving this command, C-Boot ROM will boot from the BOOT_FROM_SPI 0x0000 0004 Control Subsystem SPI interface. Upon receiving this command, C-Boot ROM will boot from the BOOT_FROM_I2C 0x0000 0005 Control Subsystem I2 C interface. Upon receiving this command, C-Boot ROM will boot from the BOOT_FROM_PARALLEL 0x0000 0006 Control Subsystem GPIO. The boot process can be considered completed once the Cortex-M3 and Cf20;BACKGROUND-COLOR:#4ae2f7">28x are both running out of their respective application programs. Note that following the boot sequence, the C-Bootloader is still available to interpret and act upon an assortment of IPC commands that can be issued from the Master Subsystem to perform a variety of configuration, housekeeping, and other functions. See the Concerto Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Technical Reference Manual (literature number SPRUH22) for additional information on Concerto boot modes, IPC commands, and the underlying boot philosophy. 40 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.9 Internal Voltage Regulation and Power-On-Reset Functionality While Concerto's analog functions draw power from a single dedicated external power source—VDDA, its digital circuits are powered by three separate rails: 3.3-V VDDIO, 1.8-V VDD18, and 1.2-V VDD12. This section describes the sourcing, regulation, and POR functionality for these three digital power rails. Concerto devices can be internally divided into an Analog Subsystem and a Digital Subsystem (having the Cortex-M3-based Master Subsystem and the Cf20;BACKGROUND-COLOR:#4ae2f7">28x-based Control Subsystem). The Digital Subsystem uses VDD12 to power the two processors, internal memory, and peripherals. The Analog Subsystem uses VDD18 to power the digital logic associated with the analog functions. Both Digital and Analog Subsystems share a common VDDIO rail to power their 3.3-V I/O buffers through which Concerto's digital signals communicate with the outside world. The Analog and Digital Subsystems each have their own POR circuits that operate independently. With the ARS and XRS reset pins externally tied together, both systems can come out of reset together, and can also be put in reset together by driving both reset pins low. See Figure 3-6 for a snapshot of the voltage regulation and POR functions provided within Concerto's Analog and Digital Subsystems. 3.9.1 Analog Subsystem's Internal 1.8-V VREG The internal 1.8-V Voltage Regulator (VREG) generates VDD18 power from VDDIO. The 1.8-V VREG is enabled by pulling the VREG18EN pin to a low state. When enabled, the 1.8V VREG provides 1.8 V to digital logic associated with the analog functions of the Analog Subsystem. When the internal 1.8-V VREG function is enabled, the 1.8 V power no longer has to be provided externally; however, a 1.2-?F (10% tolerance) capacitor is required for each VDD18 pin to stabilize the internally generated voltages. These load capacitors are not required if the internal 1.8-V VREG is disabled, and the 1.8 V is provided from an external supply. Note that while removing the need for an external power supply, enabling the internal VREG might affect the VDDIO power consumption. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 41 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 3-6. Voltage Regulation and Monitoring 42 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.9.2 Digital Subsystem's Internal 1.2-V VREG The internal 1.2-V VREG generates VDD12 power from VDDIO. The 1.2-V VREG is enabled by pulling the VREG12EN pin to a low state. When enabled, the 1.2-V VREG internally provides 1.2 V to digital logic associated with the processors, memory, and peripherals of the Digital Subsystem. When the internal 1.2-V VREG function is enabled, the 1.2 V power no longer has to be provided externally; however, the minimum and maximum capacitance required for each VDD12 pin to stabilize the internally generated voltages are 250 nF and 750 nF, respectively. These load capacitors are not required if the internal 1.2-V VREG is disabled and the 1.2 V is provided from an external supply. Note that while removing the need for an external power supply, enabling the internal VREG might affect the VDDIO power consumption. 3.9.3 Analog and Digital Subsystems' Power-On-Reset Functionality The Analog and Digital Subsystems' each have a POR circuit that creates a clean reset throughout the device enabling glitchless GPIOs during the power-on procedure. The POR function keeps both ARS and XRS driven low during device power up. While in most applications, the POR generated reset has a long enough duration to also reset other system ICs, some applications may require a longer lasting pulse. In these cases, the ARS and XRS reset pins (which are open-drain) can also be driven low to match the time the device is held in reset state with the rest of the system. When POR drives the the ARS and XRS pins low, the POR also resets the digital logic associated with both subsystems and puts the GPIO pins in a high impendance state. In addition to the POR reset, the Digital Subsystem's Resets block also receives reset inputs from the NVIC, the Cortex-M3 Watchdogs (0, 1), and from the Cortex-M3 NMI Watchdog. The resulting reset output signal is then fed back to the XRS pin after being AND-ed with the POR reset (see Figure 3-6). On a related note, only the Master Subsystem comes out of reset state immediately following a device power up. The Control and Analog Subsystems continue to be held in reset until the Master Processor (Cortex-M3) brings them out of reset by writing a "1" to the M3RSNIN and ACIBRST bits of the CRESCNF Register (see Figure 3-6). 3.9.4 Connecting ARS and XRS Pins In most Concerto applications, TI recommends that the ARS and XRS pins be tied together by external means such as through a signal trace on a PCB board. Tying the ARS and XRS pins together ensures that all reset sources will cause both the Analog and Digital Subsystems to enter the reset state together, regardless of where the reset condition occurs. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 43 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.10 Input Clocks and PLLs Concerto devices have multiple input clock pins from which all internal clocks and the output clock are derived. Figure 3-7 shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 and XCLKIN. Figure 3-7. Connecting Input Clocks to a Concerto Device 3.10.1 Internal Oscillator (Zero-Pin) Each Concerto device contains a zero-pin internal oscillator. This oscillator outputs two fixed-frequency clocks: 10MHZCLK and 32KHZCLK. These clocks are not configurable by the user and should not be used to clock the device during normal operation. They are used inside the Master Subsystem to implement low-power modes. The 10MHZCLK is also used by the Missing Clock Detect circuit. 44 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC) The main oscillator circuit connects to an external crystal through pins X1 and X2. If a resonator is used (version of a crystal with built-in load capacitors), its ground terminal should be connected to the pin VSSOSC (not board ground). The VSSOSC pin should also be used to ground the external load capacitors connected to the two crystal terminals as shown in Figure 3-7. 3.10.3 External Oscillators (Pins X1 and XCLKIN) Concerto has two pins (X1 and XCLKIN) into which a single-ended clock can be driven from external oscillators or other clock sources. When connecting an external clock source through the X1 terminal, the X2 terminal should be left unconnected. Most internal clocks of this device are derived from the X1 clock input (or X1/X2 crystal) . The XCLKIN clock is only used by the USB PLL and CAN peripherals. Figure 3-7 shows how to connect external oscillators to the X1 and XCLKIN terminals. When connecting an external oscillator, use good design practices to minimize EMI as well as clock jitter induced by external noise sources. Minimize the loop area formed between the forward current path (from the oscillator OUT terminal to the MCU X1 or XCLKIN terminal) and the return path (from the MCU VSS terminal to the oscillator GND terminal). Locate the external oscillator as close to the MCU as practical. Ideally, the return ground trace should be an isolated trace directly underneath the forward trace or run adjacent to the trace on the same layer. Spacing should be kept minimal, with any other nearby traces double-spaced away, so that the electromagnetic fields created by the two opposite currents cancel each other out as much as possible, thus reducing parasitic inductances that radiate EMI. 3.10.4 Main PLL The Main PLL uses the reference clock from pins X1 (external oscillator) or X1/X2 (external crystal/resonator). The input clock is multiplied by an integer multiplier and a fractional multiplier as selected by the SPLLIMULT and SPLLFMULT fields of the SYSPLLMULT register. For example, to achieve PLL multiply of f20;BACKGROUND-COLOR:#4ae2f7">28.5, the integer multiplier should be set to f20;BACKGROUND-COLOR:#4ae2f7">28, and the fractional multiplier to 0.5. The output clock from the Main PLL must be between 150 MHz and 550 MHz. The PLL output clock is then divided by 2 before entering a mux that selects between this clock and the PLL input clock – OSCCLK (used in PLL bypass mode). The PLL bypass mode is selected by setting the SPLLIMULT field of the SYSPLLMULT register to 0. The output clock from the mux next enters a divider controlled by the SYSDIVSEL register, after which the output clock becomes the PLLSYSCLK. Figure 3-8 shows the Main PLL function and configuration examples. Table 3-20 to Table 3-23 list the integer multiplier configuration values. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 45 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 3-8. Main PLL 46 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-20. Main PLL Integer Multiplier Configuration (Bypass PLL to x 31) SPLLIMULT(6:0) MULT VALUE 0000000 b Bypass PLL 0000001 b x 1 0000010 b x 2 0000011 b x 3 0000100 b x 4 0000101 b x 5 0000110 b x 6 0000111 b x 7 0001000 b x 8 0001001 b x 9 0001010 b x 10 0001011 b x 11 0001100 b x 12 0001101 b x 13 0001110 b x 14 0001111 b x 15 0010000 b x 16 0010001 b x 17 0010010 b x 18 0010011 b x 19 0010100 b x 20 0010101 b x 21 0010110 b x 22 0010111 b x 23 0011000 b x 24 0011001 b x 25 0011010 b x 26 0011011 b x 27 0011100 b x f20;BACKGROUND-COLOR:#4ae2f7">28 0011101 b x 29 0011110 b x 30 0011111 b x 31 Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 47 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-21. Main PLL Integer Multiplier Configuration (x 32 to x 63) SPLLIMULT(6:0) MULT VALUE 0100000 b x 32 0100001 b x 33 0100010 b x 34 0100011 b x 35 0100100 b x 36 0100101 b x 37 0100110 b x 38 0100111 b x 39 0101000 b x 40 0101001 b x 41 0101010 b x 42 0101011 b x 43 0101100 b x 44 0101101 b x 45 0101110 b x 46 0101111 b x 47 0110000 b x 48 0110001 b x 49 0110010 b x 50 0110011 b x 51 0110100 b x 52 0110101 b x 53 0110110 b x 54 0110111 b x 55 0111000 b x 56 0111001 b x 57 0111010 b x 58 0111011 b x 59 0111100 b x 60 0111101 b x 61 0111110 b x 62 0111111 b x 63 48 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-22. Main PLL Integer Multiplier Configuration (x 64 to x 95) SPLLIMULT(6:0) MULT VALUE 1000000 b x 64 1000001 b x 65 1000010 b x 66 1000011 b x 67 1000100 b x 68 1000101 b x 69 1000110 b x 70 1000111 b x 71 1001000 b x 72 1001001 b x 73 1001010 b x 74 1001011 b x 75 1001100 b x 76 1001101 b x 77 1001110 b x 78 1001111 b x 79 1010000 b x 80 1010001 b x 81 1010010 b x 82 1010011 b x 83 1010100 b x 84 1010101 b x 85 1010110 b x 86 1010111 b x 87 1011000 b x 88 1011001 b x 89 1011010 b x 90 1011011 b x 91 1011100 b x 92 1011101 b x 93 1011110 b x 94 1011111 b x 95 Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 49 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-23. Main PLL Integer Multiplier Configuration (x 96 to x 127) SPLLIMULT(6:0) MULT VALUE 1100000 b x 96 1100001 b x 97 1100010 b x 98 1100011 b x 99 1100100 b x 100 1100101 b x 101 1100110 b x 102 1100111 b x 103 1101000 b x 104 1101001 b x 105 1101010 b x 106 1101011 b x 107 1101100 b x 108 1101101 b x 109 1101110 b x 110 1101111 b x 111 1110000 b x 112 1110001 b x 113 1110010 b x 114 1110011 b x 115 1110100 b x 116 1110101 b x 117 1110110 b x 118 1110111 b x 119 1111000 b x 120 1111001 b x 121 1111010 b x 122 1111011 b x 123 1111100 b x 124 1111101 b x 125 1111110 b x 126 1111111 b x 127 3.10.5 USB PLL The USB PLL uses the reference clock selectable between the input clock arriving at the XCLKIN pin, or the internal OSCCLK (originating from the external crystal or oscillator via the X1/X2 pins). An input mux selects the source of the USB PLL reference based on the UPLLCLKSRC bit of the UPLLCTL Register (see Figure 3-9). The input clock is multiplied by an integer multiplier and a fractional multiplier as selected by the UPLLIMULT and UPLLFMULT fields of the UPLLMULT register. For example, to achieve PLL multiply of f20;BACKGROUND-COLOR:#4ae2f7">28.5, the integer multiplier should be set to f20;BACKGROUND-COLOR:#4ae2f7">28, and the fractional multiplier to 0.5. The output clock from the USB PLL must always be 240 MHz. The PLL output clock is then divided by 4—resulting in 60 MHz that the USB needs—before entering a mux that selects between this clock and the PLL input clock (used in the PLL bypass mode). The PLL bypass mode is selected by setting the UPLLIMULT field of the UPLLMULT register to 0. The output clock from the mux becomes the USBPLLCLK (there is not another clock divider). Figure 3-9 shows the USB PLL function and configuration examples. Table 3-24 and Table 3-25 list the integer multiplier configuration values. 50 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 3-9. USB PLL Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 51 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-24. USB PLL Integer Multiplier Configuration (Bypass PLL to x 31) SPLLIMULT(5:0) MULT VALUE 000000 b Bypass PLL 000001 b x 1 000010 b x 2 000011 b x 3 000100 b x 4 000101 b x 5 000110 b x 6 000111 b x 7 001000 b x 8 001001 b x 9 001010 b x 10 001011 b x 11 001100 b x 12 001101 b x 13 001110 b x 14 001111 b x 15 010000 b x 16 010001 b x 17 010010 b x 18 010011 b x 19 010100 b x 20 010101 b x 21 010110 b x 22 010111 b x 23 011000 b x 24 011001 b x 25 011010 b x 26 011011 b x 27 011100 b x f20;BACKGROUND-COLOR:#4ae2f7">28 011101 b x 29 011110 b x 30 011111 b x 31 52 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-25. USB PLL Integer Multiplier Configuration (x 32 to x 63) SPLLIMULT(5:0) MULT VALUE 100000 b x 32 100001 b x 33 100010 b x 34 100011 b x 35 100100 b x 36 100101 b x 37 100110 b x 38 100111 b x 39 101000 b x 40 101001 b x 41 101010 b x 42 101011 b x 43 101100 b x 44 101101 b x 45 101110 b x 46 101111 b x 47 110000 b x 48 110001 b x 49 110010 b x 50 110011 b x 51 110100 b x 52 110101 b x 53 110110 b x 54 110111 b x 55 111000 b x 56 111001 b x 57 111010 b x 58 111011 b x 59 111100 b x 60 111101 b x 61 111110 b x 62 111111 b x 63 Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 53 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.11 Master Subsystem Clocking The internal PLLSYSCLK clock, normally used as a source for all Master Subsystem clocks, is a divided- down output of the Main PLL or X1 external clock input, as defined by the SPLLCKEN bit of the SYSPLLCTL register. There is also a second oscillator that internally generates two clocks: 32KHZCLK and 10MHZCLK. The 10MHZCLK is used by the Missing Clock Circuit to detect a possible absence of an external clock source to the Main Oscillator that drives the Main PLL. Detection of a missing clock results in a substitution of the 10MHZCLK for the PLLSYSCLK. The CLKFAIL signal is also sent to the NMI Block and the Control Subsystem where this signal can trip the ePWM peripherals. The 32KHZCLK and 10MHZCLK clocks are also used by the Cortex-M3 Subsystem as possible sources for the Deep Sleep Clock. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor has read access. The Cf20;BACKGROUND-COLOR:#4ae2f7">28x can request write access to the above registers through the CLKREQEST register. Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register. The Master Subsystem operates in one of three modes: Run Mode, Sleep Mode, or Deep Sleep Mode. Table 3-26 shows the Master Subsystem low-power modes and their effect on both CPUs, clocks, and peripherals. Figure 3-10 shows the Cortex-M3 clocks and the Master Subsystem low-power modes. Table 3-26. Master Subsystem Low-Power Modes Register Used to Cortex-M3 State of Clock to Clock to Gate Clocks Main USB Clock to Shared Low-Power Cortex-M3 Cortex-M3 Clock to Cf20;BACKGROUND-COLOR:#4ae2f7">28x Analog to Cortex- PLL PLL Resources Mode CPU Peripherals Subsystem M3 Peripherals Run Active M3SSCLK(1) RCGC On On PLLSYSCLK(2) PLLSYSCLK(2) ASYSCLK(3) RCGC or Sleep Stopped M3SSCLK(1) On On PLLSYSCLK(2) PLLSYSCLK(2) ASYSCLK(3) SCGC(4) RCGC or Deep Sleep Stopped M3DSDIVCLK(5) Off Off Off Off Off DCGC(4) (1) PLLSYSCLK or OSCCLK divided-down per the M3SSDIVSEL register. In case of a missing source clock, M3SSCLK becomes 10MHZCLK divided-down per the M3SSDIVSEL register. (2) PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK. (3) PLLSYSCLK or OSCCLK divided-down per the CCLKCTL register. In case of a missing source clock, ASYSCLK becomes 10MHZCLK. (4) Depends on the ACG bit of the RCC register. (5) 32KHZCLK or 10MHZCLK or OSCCLK chosen/divided-down per the DSLPCLKCFG register, then again divided by the M3SSDIVSEL register (source determined inside the DSLPCLKCFG register). Figure 3-11 shows the system clock/PLL. 54 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 3-10. Cortex-M3 Clocks and Low-Power Modes Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 55 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 3-11. System Clock/PLL 56 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.11.1 Cortex-M3 Run Mode In Run Mode, the Cortex-M3 processor, memory, and most of the peripherals are clocked by the M3SSCLK, which is a divide-down version of the PLLSYSCLK (from Main PLL). The USB is clocked from a dedicated USB PLL, the CAN peripherals are clocked by M3SSCLK, OSCCLK, or XCLKIN, and one of two watchdogs (WDOG1) is also clocked by the OSCCLK. Clock selection for these peripherals is accomplished via corresponding peripheral configuration registers. Clock gating for individual peripherals is defined inside the RCGS register. RCGS, SCGS, and DCGS clock-gating settings only apply to peripherals that are enabled in a corresponding DC (Device Configuration) register. Execution of the WFI instruction (Wait-for-Interrupt) shuts down the HCLK to the Cortex-M3 CPU and forces the Cortex-M3 Subsystem into Sleep or Deep Sleep low-power mode, depending on the state of the SLEEPDEEP bit of the Cortex-M3 SYSCTRL register. To come out of a low-power mode, any properly configured interrupt event terminates the Sleep or Deep Sleep Mode and returns the Cortex-M3 processor/subsystem to Run Mode. 3.11.2 Cortex-M3 Sleep Mode In Sleep Mode, the Cortex-M3 processor and memory are prevented from clocking, and thus the code is no longer executing. The gating for the peripheral clocks may change based on the ACG bit of the RCC register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in Run Mode); and when ASC = 1, the clock gating comes from the SCGS register. RCGS and SCGS clock- gating settings only apply to peripherals that are enabled in a corresponding DC register. Peripheral clock frequency for the enabled peripherals in Sleep Mode is the same as during the Run Mode. Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Sleep Mode depends on the SLEEPEXIT bit of the SYSCTRL register. When the SLEEPEXIT bit is 1, the processor will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that, the processor goes back to Sleep Mode. When the SLEEPEXIT bit is 0, the processor wakes up permanently (for the ISR and thereafter). Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 57 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.11.3 Cortex-M3 Deep Sleep Mode In Deep Sleep Mode, the Cortex-M3 processor and memory are prevented from clocking and thus the code is no longer executing. The Main PLL, USB PLL, ASYSCLK to the Analog Subsystem, and input clock to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU and Shared Resources are turned off. The gating for the peripheral clocks may change based on the ACG bit of the RCC register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in Run Mode); and when ASC = 1, the clock gating comes from the DCGS register. RCGS and DCGS clock gating settings only apply to peripherals that are enabled in a corresponding DC register. Peripheral clock frequency for the enabled peripherals in Deep Sleep Mode is different from the Run Mode. One of three sources for the Deep Sleep clocks (32KHZCLK, 10MHZCLK, or OSCLK) is selected with the DSOSCSRC bits of the DSLPCLKCFG register. This clock is divided-down according to DSDIVOVRIDE bits of the DSLPCLKCFG register. The output of this Deep Sleep Divider is further divided-down per the M3SSDIVSEL bits of the D3SSDIVSEL register to become the Deep Sleep Clock. If 32KHXCLK or 10MHZCLK is selected in Deep Sleep mode, the internal oscillator circuit (that generates OSCCLK) is turned off. The Cortex-M3 processor should enter the Deep Sleep mode only after first confirming that the Cf20;BACKGROUND-COLOR:#4ae2f7">28x is already in the STANDBY mode. Typically, just before entering the STANDBY mode, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x will record in the CLPMSTAT that it is about to do so. The Cortex-M3 processor can read the CLPMSTAT register to check if the Cf20;BACKGROUND-COLOR:#4ae2f7">28x is in STANDBY mode, and only then should the Cortex-M3 processor go into Deep Sleep. The reason for the Cortex-M3 processor to confirm that the Cf20;BACKGROUND-COLOR:#4ae2f7">28x is in STANDBY mode before the Cortex-M3 processor enters the Deep Sleep mode is that the Deep Sleep mode shuts down the clock to Cf20;BACKGROUND-COLOR:#4ae2f7">28x and its peripherals, and if this clock shutdown is not expected by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x, unintended consequences could result for some of the Cf20;BACKGROUND-COLOR:#4ae2f7">28x control peripherals. Deep Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Deep Sleep Mode depends on the SLEEPEXIT bit of the SYSCTRL register. When the SLEEPEXIT bit is 1, the processor will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that, the processor goes back to Deep Sleep Mode. When the SLEEPEXIT bit is 0, the processor wakes up permanently (for the ISR and thereafter). 58 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.12 Control Subsystem Clocking The CLKIN input clock to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor is normally a divided-down output of the Main PLL or X1 external clock input. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor has read access. The Cf20;BACKGROUND-COLOR:#4ae2f7">28x can request write access to the above registers through the CLKREQEST register. The Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register. Individual Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals can be turned on or off by gating Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK to those peripherals, which is done via the CPCLKCR0,2,3 registers. The Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor outputs two clocks: Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK and Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK. The Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK is used by Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals, Cf20;BACKGROUND-COLOR:#4ae2f7">28x Timer 0, Cf20;BACKGROUND-COLOR:#4ae2f7">28x Timer 1, and Cf20;BACKGROUND-COLOR:#4ae2f7">28x Timer 2. Cf20;BACKGROUND-COLOR:#4ae2f7">28x Timer 2 can also be clocked by OSCCLK or 10MHZCLK (see Figure 3-12). The Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK is used by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU, FPU, VCU, and PIE. The Control Subsystem operates in one of three modes: Normal Mode, IDLE Mode, or STANDBY Mode. Table 3-27 shows the Control Subsystem low-power modes and their effect on the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU, clocks, and peripherals. Figure 3-12 shows the Control Subsystem clocks and low-power modes. Table 3-27. Control Subsystem Low-Power Modes(1) Registers Used to Gate Cf20;BACKGROUND-COLOR:#4ae2f7">28x Low-Power Mode State of Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK(2) Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK(3) Clocks to Cf20;BACKGROUND-COLOR:#4ae2f7">28x Peripherals Normal Active On On CPCLKCR0,1,3 IDLE Stopped Off On CPCLKCR0,1,3 STANDBY Stopped Off Off N/A (1) The input clock to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU is PLLSYSCLK from the Master Subsystem. This clock is turned off when the Master Subsystem enters the Deep Sleep mode. (2) Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK is an output from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU. Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK clocks the Cf20;BACKGROUND-COLOR:#4ae2f7">28x FPU, VCU, and PIE. (3) Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK is an output from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU. Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK clocks Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals. 3.12.1 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Normal Mode In Normal Mode, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor, Local Memory, and Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals are clocked by the Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK, which is derived from the Cf20;BACKGROUND-COLOR:#4ae2f7">28CLKIN input clock to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor. The FPU, VCU, and PIE are clocked by the Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK, which is also derived from the Cf20;BACKGROUND-COLOR:#4ae2f7">28CLKIN. Timer 2 can also be clocked by the TMR2CLK, which is a divided-down version of one of three source clocks—Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK, OSCCLK, and 10MHZCLK—as selected by the CLKCTL register. Additionally, the LOSPCP register can be programmed to provide a dedicated clock (Cf20;BACKGROUND-COLOR:#4ae2f7">28LSPCLK) to the SCI, SPI, and McBSP peripherals. Clock gating for individual peripherals is defined inside the CPCLKCR0,1,3 registers. Execution of the IDLE instruction stops the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor from clocking and activates the IDLES signal. The IDLES signal is gated with two LPM bits of the CPCLKCR0 register to enter the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Subsystem into IDLE mode or STANDBY Mode. 3.12.2 Cf20;BACKGROUND-COLOR:#4ae2f7">28x IDLE Mode In IDLE Mode, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor stops executing instructions and the Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK is turned off. The Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK continues to run. Exit from IDLE Mode is accomplished by any enabled interrupt or the Cf20;BACKGROUND-COLOR:#4ae2f7">28NMIINT (Cf20;BACKGROUND-COLOR:#4ae2f7">28x non-maskable interrupt). Upon exit from IDLE Mode, the Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK is restored. If LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor starts fetching instructions from a location immediately following the IDLE instruction that originally triggered the IDLE Mode. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 59 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 3-12. Cf20;BACKGROUND-COLOR:#4ae2f7">28x Clocks and Low-Power Modes 60 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.12.3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x STANDBY Mode In STANDBY Mode, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor stops executing instructions and the Cf20;BACKGROUND-COLOR:#4ae2f7">28CLKIN, Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK, and Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK are turned off. Exit from STANDBY Mode is accomplished by 1 of 62 GPIOs from the GPIO_MUX1 block, or MTOCIPCINT1 (interrupt from MTOC IPC peripheral). The wakeup GPIO selected inside the GPIO_MUX block enters the Qualification Block as the LPMWAKE signal. Inside the Qualification Block, the LPMWAKE signal is sampled per the QUALSTDBY bits (bits [7:2] of the CPCLKCR0 register) before propagating into the wake request logic. Cortex-M3 should use CLPMSTAT register bits to tell the Cf20;BACKGROUND-COLOR:#4ae2f7">28x to go into STANDBY mode before going into Deep Sleep mode. Otherwise, the clock to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x will be turned off suddenly when the control software is not expecting this clock to shut off. When the device is in Deep Sleep/STANDBY mode, wake- up should happen only from the Master Subsystem, since all Cf20;BACKGROUND-COLOR:#4ae2f7">28x clocks are off (Cf20;BACKGROUND-COLOR:#4ae2f7">28CLKIN, Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK, Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK), thus preventing the Cf20;BACKGROUND-COLOR:#4ae2f7">28x from waking up first. Upon exit from STANDBY Mode, the Cf20;BACKGROUND-COLOR:#4ae2f7">28CLKIN, Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK, and Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK are restored. If the LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor starts fetching instructions from a location immediately following the IDLE instruction that originally triggered the STANDBY Mode. NOTE For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function is available on silicon revision 0 devices (GPIO and other functions listed in Table 4-1 are not available). Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 61 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.13 Analog Subsystem Clocking The Analog Subsystem is clocked by ASYSCLK, which is a divided-down version of the PLLSYSCLK as defined by CLKDIV bits of the CCLKCTL register. The CCLKCTL register is exclusively accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x processor. The CCLKCTL register is reset by ASYSRST, which is derived from two Analog Subsystem resets—ACIBRST and SRXRST. Therefore, while normally the Cf20;BACKGROUND-COLOR:#4ae2f7">28x controls the frequency of ASYSCLK, it is possible for the Cortex-M3 software to restore the ASYSCLK to its default value by resetting the Analog Subsystem. The ASYSCLK is shut down when the Cortex-M3 processor enters the Deep Sleep mode. 3.14 Shared Resources Clocking The IPC, Shared RAMs, and Message RAMs are clocked by PLLSYSCLK. EPI is clocked by M3SSCLK. The PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK. Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore, EPI is clocked by M3SSCLK. 3.15 Loss of Input Clock (NMI Watchdog Function) The Concerto devices use two type of input clocks. The main clock, for clocking most of the digital logic of the Master, Control, and Analog subsystems, enters the chip through pins X1 and X2 when using external crystal or just pin X1 when using an external oscillator. The second clock enters the chip through the XCLKIN pin and this second clock can be used to clock the USB PLL and CAN peripherals. Only the main clock has a built-in Missing Clock Detection circuit to recognize when the clock source vanishes and to enable other chip components to take corrective or recovery action from such event (see Figure 3-13). The Missing Clock Detection circuit itself is clocked by the 10MHZCLK (from an internal zero-pin oscillator) so that, if the main clock disappears, the circuit is still working. Immediately after detecting a missing source clock, the Missing Clock Detection circuit outputs the CLOCKFAIL signal to the Cortex-M3 NMI circuit, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x NMI, ePWM peripherals, and the PLLSYSCLK mux. When the PLLSYSCLK mux senses an active CLOCKFAIL signal, the PLLSYSCLK mux revives the PLLSYSCLK using the 10MHZCLK. Simultaneously, the ePWM peripherals can use the CLOCKFAIL signal to stop down driving motor control outputs. The NMI blocks respond to the CLOCKFAIL signal by sending an NMI interrupt to a corresponding CPU, while starting the associated NMI watchdog counter. If the software does not respond to the clock-fail condition, the watchdog timers will overflow, resulting in the device reset. If the software does react to the NMI, the software can prevent the impending reset by disabling the watchdog timers, and then the software can initiate necessary corrective action such as switching over to an alternative clock source (if available) or the software can initiate a shut-down procedure for the system. 62 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 3-13. Missing Clock Detection Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 63 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.16 GPIOs and Other Pins Most Concerto external pins are shared among many internal peripherals. This sharing of pins is accomplished through several I/O muxes where a specific physical pin can be assigned to selected signals of internal peripherals. Most of the I/O pins of the Concerto MCU can also be configured as programmable GPIOs. Exceptions include the X1 and X2 oscillator inputs; the XRS digital reset and ARS analog reset; the VREG12EN and VREG18EN internal voltage regulator enables; and five JTAG pins. The 74 primary GPIOs are grouped in 2 programmable blocks: GPIO_MUX1 block (66 pins) and GPIO_MUX2 block (8 pins). Additionally, eight secondary GPIOs are available through the AIO_MUX1 block (four pins) and AIO_MUX2 block (four pins). Figure 3-14 shows the GPIOs and other pins. 3.16.1 GPIO_MUX1 Sixty-six pins of the GPIO_MUX1 block can be selectively mapped through corresponding sets of registers to all Cortex-M3 peripherals, to all Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals, to 66 General-Purpose Inputs, to 66 General- Purpose Outputs, or a mixture of all of the above. Sixty-two pins of GPIO_MUX1 (GPIO0–GPIO63 minus GPIO39 and GPIO44) can also be mapped to 12 ePWM Trip Inputs, 6 eCAP inputs, 3 External Interrupts to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x PIE, and the Cf20;BACKGROUND-COLOR:#4ae2f7">28x STANDBY Mode Wakeup signal (LMPWAKE). Additionally, each GPIO_MUX1 pin can have a pullup enabled or disabled. By default, all pullups and outputs are disabled on reset, and all pins of the GPIO_MUX1 block are mapped to Cortex-M3 peripherals (and not to Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals). Figure 3-15 shows the internal structure of GPIO_MUX1. The blue blocks represent the Master Subsystem side of GPIO_MUX1, and the green blocks are the Control Subsystem side. The grey block in the center, Pin-Level Mux, is where the GPIO_MUX1 pins are individually assigned between the two subsystems, based on how the configuration registers are programmed in the blue and green blocks (see Figure 3-16 for the configuration registers). Pin-Level Mux assigns Master Subsystem peripheral signals, Control Subsystem peripheral signals, or GPIOs to the 66 GPIO_MUX1 pins. In addition to connecting peripheral I/Os of the two subsystems to pins, the Pin-Level Mux also provides other signals to the subsystems: XCLKIN and GPIO[A:J] IRQ signals to the Master Subsystem, plus GPTRIP[12:1] and GPI[63:0] signals to the Control Subsystem. XCLKIN carries a clock from an external pin to USB PLL and CAN modules. The nine GPIO[A:J] IRQ signals are interrupt requests from selected external pins to the NVIC interrupt controller. The 12 GPTRIP[12:1] signals carry trip events from selected external pins to Cf20;BACKGROUND-COLOR:#4ae2f7">28x control peripherals—ePWM, eCAP, and eQEP. Sixty-four GPI signals go to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x LPM GPIO Select block where one of them can be selected to wake up the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU from Low-Power Mode. Sixty-six (66) GPI signals go to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x QUAL block where they can be configured with a qualification sampling period (see Figure 3-16). The configuration registers for the muxing of Master Subsystem peripherals are organized in nine sets (A–J), with each set being responsible for eight pins. These nine sets of registers are programmable by the Cortex-M3 CPU via the AHB bus or the APB bus. The configuration register for the muxing of Control Subsystem peripherals are organized in three sets (A–C), with each set being responsible for up to 32 pins. These registers are programmable by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU via the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU bus. Figure 3-16 shows set A of the Master Subsystem GPIO configuration registers, set A of the Control Subsystem registers, and the muxing logic for one GPIO pin as driven by these registers. 64 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 3-14. GPIOs and Other Pins Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 65 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 3-15. GPIO_MUX1 Block 66 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 3-16. GPIO_MUX1 Pin Mapping Through Register Set A Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 67 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn For each of the 8 pins in set A of the Cortex-M3 GPIO registers, register GPIOPCTL selects between 1 of 11 possible primary Cortex-M3 peripheral signals, or 1 of 4 possible alternate peripheral signals. Register GPIOAPSEL then picks one output to propagate further along the muxing chain towards a given pin. The input takes the reverse path. See Table 3-f20;BACKGROUND-COLOR:#4ae2f7">28 and Table 3-29 for the mapping of Cortex-M3 peripheral signals to GPIO_MUX1 pins. Similarly, on the Cf20;BACKGROUND-COLOR:#4ae2f7">28x side, GPAMUX1 and GPAMUX2 registers select 1 of 4 possible Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripheral signals for each of 32 pins of set A. The selected Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripheral output then propagates further along the muxing chain towards a given pin. The input takes the reverse path. See Table 3-30 for the mapping of Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripheral signals to GPIO_MUX1 pins. In addition to passing mostly digital signals, four GPIO_MUX1 pins can also be assigned to analog signals. The GPIO Analog Mode Select (GPIOAMSEL) Register is used to assign four pins to analog USB signals. PF6_GPIO38 becomes USB0VBUS, PG2_GPIO42 becomes USB0DM, PG5_GPIO45 becomes USB0DP, and PG6_GPIO46 becomes USB0ID. When analog mode is selected, these four pins are not available for digital GPIO_MUX1 options as described above. Another special case is the External Oscillator Input signal (XCLKIN). This signal, available through pin PJ7_GPIO63, is directly tied to USBPLLCLK (clock input to USB PLL) and two CAN modules. XCLKIN is always available at these modules where it can be selected through local registers. NOTE For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function is available on silicon revision 0 devices (GPIO and other functions listed in Table 4-1 are not available). 68 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-f20;BACKGROUND-COLOR:#4ae2f7">28. GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1) Analog M3 M3 M3 M3 M3 M3 M3 M3 M3 M3 M3 Device Mode Primary Primary Primary Primary Primary Primary Primary Primary Primary Primary Primary Pin Name (USB Pins) Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 Mode 10 Mode 11 – PA0_GPIO0 U0RX I2C1SCL U1RX – – – PA1_GPIO1 U0TX I2C1SDA U1TX – – – PA2_GPIO2 SSI0CLK – MIITXD2 – PA3_GPIO3 SSI0FSS – MIITXD1 – PA4_GPIO4 SSI0RX – MIITXD0 – CAN0RX – PA5_GPIO5 SSI0TX – MIIRXDV – CAN0TX – PA6_GPIO6 I2C1SCL CCP1 MIIRXCK – – CAN0RX – USB0EPEN – – – – PA7_GPIO7 I2C1SDA CCP4 MIIRXER – – CAN0TX CCP3 USB0PFLT – – – – PB0_GPIO8 CCP0 – – – U1RX – PB1_GPIO9 CCP2 – – CCP1 U1TX – PB2_GPIO10 I2C0SCL – – CCP3 CCP0 – – USB0EPEN – – – – PB3_GPIO11 I2C0SDA USB0PFLT – – – – PB4_GPIO12 – – – U2RX CAN0RX – U1RX EPI0S23 – – – – PB5_GPIO13 – CCP5 CCP6 CCP0 CAN0TX CCP2 U1TX EPI0S22 – – – – PB6_GPIO14 CCP1 CCP7 – – – CCP5 – EPI0S37(2) – – – – PB7_GPIO15 – – – EXTNMI – – MIIRXD1 EPI0S36(2) – – – – PD0_GPIO16 – CAN0RX – U2RX U1RX CCP6 MIIRXDV – – – – – PD1_GPIO17 – CAN0TX – U2TX U1TX CCP7 MIITXER – – CCP2 – – PD2_GPIO18 U1RX CCP6 – CCP5 – – – EPI0S20 – – – – PD3_GPIO19 U1TX CCP7 – CCP0 – – – EPI0S21 – – – – PD4_GPIO20 CCP0 CCP3 – MIITXD3 EPI0S19 – – PD5_GPIO21 CCP2 CCP4 – MIITXD2 – – – – U2RX EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 – – PD6_GPIO22 – – – MIITXD1 – – – – U2TX EPI0S29 – – PD7_GPIO23 – – CCP1 MIITXD0 EPI0S30 – – PE0_GPIO24 – SSI1CLK CCP3 – – – – EPI0S8 USB0PFLT – – – PE1_GPIO25 – SSI1FSS – CCP2 CCP6 – – EPI0S9 – – – – PE2_GPIO26 CCP4 SSI1RX – – CCP2 – – EPI0S24 – – – – PE3_GPIO27 CCP1 SSI1TX – – CCP7 – – EPI0S25 – – – – PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 CCP3 – – – U2TX CCP2 MIIRXD0 EPI0S34(2) – – – – PE5_GPIO29 CCP5 EPI0S35(2) – – – – PE6_GPIO30 – PE7_GPIO31 (1) Blank fields represent Reserved functions. (2) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 69 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-f20;BACKGROUND-COLOR:#4ae2f7">28. GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1) (continued) Analog M3 M3 M3 M3 M3 M3 M3 M3 M3 M3 M3 Device Mode Primary Primary Primary Primary Primary Primary Primary Primary Primary Primary Primary Pin Name (USB Pins) Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 Mode 10 Mode 11 – PF0_GPIO32 CAN1RX – – MIIRXCK – PF1_GPIO33 CAN1TX – – MIIRXER CCP3 – – PF2_GPIO34 – – MIIPHYINTR – – – – SSI1CLK – – EPI0S32(2) – PF3_GPIO35 – – MIIMDC – – – – SSI1FSS – – EPI0S33(2) – PF4_GPIO36 CCP0 – MIIMDIO – – – – EPI0S12 SSI1RX – – – PF5_GPIO37 CCP2 – MIIRXD3 – – – – EPI0S15 SSI1TX – – USB0VBUS PF6_GPIO38 CCP1 – MIIRXD2 EPI0S38(2) PF7_GPIO39 (no pin) – PG0_GPIO40 U2RX – I2C1SCL – – – USB0EPEN EPI0S13 – – – – PG1_GPIO41 U2TX – I2C1SDA – – – – EPI0S14 – – – USB0DM PG2_GPIO42 – – MIICOL EPI0S39(2) – PG3_GPIO43 – – MIICRS PG4_GPIO44 (no pin) USB0DP PG5_GPIO45 CCP5 – MIITXEN EPI0S40(2) USB0ID PG6_GPIO46 – – MIITXCK EPI0S41(2) – PG7_GPIO47 – – MIITXER – – – – CCP5 EPI0S31 – – – PH0_GPIO48 CCP6 – MIIPHYRST – – – – EPI0S6 – – – – PH1_GPIO49 CCP7 EPI0S7 – – – – PH2_GPIO50 EPI0S1 MIITXD3 – – – PH3_GPIO51 – – – USB0EPEN – – – EPI0S0 MIITXD2 – – – PH4_GPIO52 – – – USB0PFLT – – – EPI0S10 MIITXD1 – SSI1CLK – PH5_GPIO53 EPI0S11 MIITXD0 – SSI1FSS – PH6_GPIO54 EPI0S26 MIIRXDV – SSI1RX – PH7_GPIO55 – – MIIRXCK – – – – EPI0S27 – – SSI1TX – PJ0_GPIO56 – – MIIRXER – – – – EPI0S16 – – I2C1SCL – PJ1_GPIO57 EPI0S17 USB0PFLT – I2C1SDA – PJ2_GPIO58 EPI0S18 CCP0 – – – PJ3_GPIO59 EPI0S19 – CCP6 – – PJ4_GPIO60 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 – CCP4 – – PJ5_GPIO61 EPI0S29 – CCP2 – – PJ6_GPIO62 EPI0S30 – CCP1 – PJ7_GPIO63/ CCP0 – XCLKIN 70 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-f20;BACKGROUND-COLOR:#4ae2f7">28. GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1) (continued) Analog M3 M3 M3 M3 M3 M3 M3 M3 M3 M3 M3 Device Mode Primary Primary Primary Primary Primary Primary Primary Primary Primary Primary Primary Pin Name (USB Pins) Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 Mode 10 Mode 11 PC0_GPIO64 (no pin) PC1_GPIO65 (no pin) PC2_GPIO66 (no pin) PC3_GPIO67 (no pin) – PC4_GPIO68 CCP5 – MIITXD3 – CCP2 CCP4 – EPI0S2 CCP1 – – – PC5_GPIO69 CCP1 – – – CCP3 USB0EPEN – EPI0S3 – – – – PC6_GPIO70 CCP3 – – – U1RX CCP0 USB0PFLT EPI0S4 – – – – PC7_GPIO71 CCP4 – – CCP0 U1TX USB0PFLT – EPI0S5 – – – Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 71 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-29. GPIO_MUX1 Pin Assignments (M3 Alternate Modes)(1) M3 M3 M3 M3 Analog Mode Device Pin Name Alternate Alternate Alternate Alternate (USB Pins) Mode 12 Mode 13 Mode 14 Mode 15 – PA0_GPIO0 – – – – – PA1_GPIO1 – – – SSI1FSS – PA2_GPIO2 – – – – – PA3_GPIO3 – – – SSI1CLK – PA4_GPIO4 – – – – – PA5_GPIO5 – – – – – PA6_GPIO6 MIITXD3 – – – – PA7_GPIO7 MIIRXD1 – – – – PB0_GPIO8 – SSI2TX CAN1TX U4TX – PB1_GPIO9 – SSI2RX – – – PB2_GPIO10 – SSI2CLK CAN1RX U4RX – PB3_GPIO11 – SSI2FSS U1RX – – PB4_GPIO12 – – CAN1TX SSI1TX – PB5_GPIO13 – – CAN1RX SSI1RX – PB6_GPIO14 MIICRS I2C0SDA U1TX SSI1CLK – PB7_GPIO15 – I2C0SCL U1RX SSI1FSS – PD0_GPIO16 MIIRXD2 SSI0TX CAN1TX USB0EPEN – PD1_GPIO17 MIICOL SSI0RX CAN1RX USB0PFLT – PD2_GPIO18 – SSI0CLK U1TX CAN0RX – PD3_GPIO19 – SSI0FSS U1RX CAN0TX – PD4_GPIO20 – – U3TX CAN1TX – PD5_GPIO21 – – U3RX CAN1RX – PD6_GPIO22 – – I2C1SDA U1TX – PD7_GPIO23 – – I2C1SCL U1RX – PE0_GPIO24 – SSI3TX CAN0RX SSI1TX – PE1_GPIO25 – SSI3RX CAN0TX SSI1RX – PE2_GPIO26 – SSI3CLK U2RX SSI1CLK – PE3_GPIO27 – SSI3FSS U2TX SSI1FSS – PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 – U0RX EPI0S38(2) USB0EPEN – PE5_GPIO29 MIITXER U0TX – USB0PFLT – PE6_GPIO30 MIIMDIO CAN0RX – – – PE7_GPIO31 MIIRXD3 CAN0TX – – – PF0_GPIO32 – I2C0SDA TRACED2 – – PF1_GPIO33 – I2C0SCL TRACED3 – – PF2_GPIO34 – – TRACECLK XCLKOUT – PF3_GPIO35 – U0TX TRACED0 – – PF4_GPIO36 – U0RX – – – PF5_GPIO37 – – – – USB0VBUS PF6_GPIO38 – – – – PF7_GPIO39 (no pin) (1) Blank fields represent Reserved functions. (2) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices. 72 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-29. GPIO_MUX1 Pin Assignments (M3 Alternate Modes)(1) (continued) M3 M3 M3 M3 Analog Mode Device Pin Name Alternate Alternate Alternate Alternate (USB Pins) Mode 12 Mode 13 Mode 14 Mode 15 – PG0_GPIO40 MIIRXD2 U4RX – – – PG1_GPIO41 MIIRXD1 U4TX – – USB0DM PG2_GPIO42 – – – – – PG3_GPIO43 MIIRXDV – TRACED1 – PG4_GPIO44 (no pin) USB0DP PG5_GPIO45 – – – – USB0ID PG6_GPIO46 – – – – – PG7_GPIO47 – – – – – PH0_GPIO48 – SSI3TX – – – PH1_GPIO49 MIIRXD0 SSI3RX – – – PH2_GPIO50 – SSI3CLK – – – PH3_GPIO51 – SSI3FSS – – – PH4_GPIO52 – U3TX – – – PH5_GPIO53 – U3RX – – – PH6_GPIO54 MIITXEN SSI0TX – – – PH7_GPIO55 MIITXCK SSI0RX – – – PJ0_GPIO56 – SSI0CLK – – – PJ1_GPIO57 MIIRXDV SSI0FSS – – – PJ2_GPIO58 MIIRXCK SSI0CLK U0TX – – PJ3_GPIO59 MIIMDC SSI0FSS U0RX – – PJ4_GPIO60 MIICOL SSI1CLK – – – PJ5_GPIO61 MIICRS SSI1FSS – – – PJ6_GPIO62 MIIPHYINTR U2RX – – PJ7_GPIO63/ – MIIPHYRST U2TX – – XCLKIN PC0_GPIO64 (no pin) PC1_GPIO65 (no pin) PC2_GPIO66 (no pin) PC3_GPIO67 (no pin) – PC4_GPIO68 – – – – – PC5_GPIO69 – – – – – PC6_GPIO70 – – – – – PC7_GPIO71 – – – – Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 73 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 3-30. GPIO_MUX1 Pin Assignments (Cf20;BACKGROUND-COLOR:#4ae2f7">28x Peripheral Modes)(1) Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cf20;BACKGROUND-COLOR:#4ae2f7">28x Analog Mode Device Pin Name Peripheral Peripheral Peripheral Peripheral (USB Pins) Mode 0 Mode 1 Mode 2 Mode 3 – PA0_GPIO0 GPIO0 EPWM1A – – – PA1_GPIO1 GPIO1 EPWM1B ECAP6 – – PA2_GPIO2 GPIO2 EPWM2A – – – PA3_GPIO3 GPIO3 EPWM2B ECAP5 – – PA4_GPIO4 GPIO4 EPWM3A – – – PA5_GPIO5 GPIO5 EPWM3B MFSRA ECAP1 – PA6_GPIO6 GPIO6 EPWM4A – EPWMSYNCO – PA7_GPIO7 GPIO7 EPWM4B MCLKRA ECAP2 – PB0_GPIO8 GPIO8 EPWM5A – ADCSOCAO – PB1_GPIO9 GPIO9 EPWM5B – ECAP3 – PB2_GPIO10 GPIO10 EPWM6A – ADCSOCBO – PB3_GPIO11 GPIO11 EPWM6B – ECAP4 – PB4_GPIO12 GPIO12 EPWM7A – – – PB5_GPIO13 GPIO13 EPWM7B – – – PB6_GPIO14 GPIO14 EPWM8A – – – PB7_GPIO15 GPIO15 EPWM8B – – – PD0_GPIO16 GPIO16 SPISIMOA – – – PD1_GPIO17 GPIO17 SPISOMIA – – – PD2_GPIO18 GPIO18 SPICLKA – – – PD3_GPIO19 GPIO19 SPISTEA – – – PD4_GPIO20 GPIO20 EQEP1A MDXA – – PD5_GPIO21 GPIO21 EQEP1B MDRA – – PD6_GPIO22 GPIO22 EQEP1S MCLKXA – – PD7_GPIO23 GPIO23 EQEP1I MFSXA – – PE0_GPIO24 GPIO24 ECAP1 EQEP2A – – PE1_GPIO25 GPIO25 ECAP2 EQEP2B – – PE2_GPIO26 GPIO26 ECAP3 EQEP2I – – PE3_GPIO27 GPIO27 ECAP4 EQEP2S – – PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 SCIRXDA – – – PE5_GPIO29 GPIO29 SCITXDA – – – PE6_GPIO30 GPIO30 – – EPWM9A – PE7_GPIO31 GPIO31 – – EPWM9B – PF0_GPIO32 GPIO32 I2CASDA SCIRXDA ADCSOCAO – PF1_GPIO33 GPIO33 I2CASCL EPWMSYNCO ADCSOCBO – PF2_GPIO34 GPIO34 ECAP1 SCIRXDA XCLKOUT – PF3_GPIO35 GPIO35 SCITXDA – – – PF4_GPIO36 GPIO36 SCIRXDA – – – PF5_GPIO37 GPIO37 ECAP2 – – USB0VBUS PF6_GPIO38 GPIO38 – – – PF7_GPIO39 (no pin) (1) Blank fields represent Reserved functions. 74 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 3-30. GPIO_MUX1 Pin Assignments (Cf20;BACKGROUND-COLOR:#4ae2f7">28x Peripheral Modes)(1) (continued) Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cf20;BACKGROUND-COLOR:#4ae2f7">28x Analog Mode Device Pin Name Peripheral Peripheral Peripheral Peripheral (USB Pins) Mode 0 Mode 1 Mode 2 Mode 3 – PG0_GPIO40 GPIO40 – – – – PG1_GPIO41 GPIO41 – – – USB0DM PG2_GPIO42 GPIO42 – – – – PG3_GPIO43 GPIO43 – – – PG4_GPIO44 (no pin) USB0DP PG5_GPIO45 GPIO45 – – – USB0ID PG6_GPIO46 GPIO46 – – – – PG7_GPIO47 GPIO47 – – – – PH0_GPIO48 GPIO48 ECAP5 – – – PH1_GPIO49 GPIO49 ECAP6 – – – PH2_GPIO50 GPIO50 EQEP1A – – – PH3_GPIO51 GPIO51 EQEP1B – – – PH4_GPIO52 GPIO52 EQEP1S – – – PH5_GPIO53 GPIO53 EQEP1I – – – PH6_GPIO54 GPIO54 SPISIMOA – EQEP3A – PH7_GPIO55 GPIO55 SPISOMIA – EQEP3B – PJ0_GPIO56 GPIO56 SPICLKA – EQEP3S – PJ1_GPIO57 GPIO57 SPISTEA – EQEP3I – PJ2_GPIO58 GPIO58 MCLKRA – EPWM7A – PJ3_GPIO59 GPIO59 MFSRA – EPWM7B – PJ4_GPIO60 GPIO60 – – EPWM8A – PJ5_GPIO61 GPIO61 – – EPWM8B – PJ6_GPIO62 GPIO62 – – EPWM9A PJ7_GPIO63/ – GPIO63 – – EPWM9B XCLKIN PC0_GPIO64 (no pin) PC1_GPIO65 (no pin) PC2_GPIO66 (no pin) PC3_GPIO67 (no pin) – PC4_GPIO68 GPIO68 – – – – PC5_GPIO69 GPIO69 – – – – PC6_GPIO70 GPIO70 – – – – PC7_GPIO71 GPIO71 – – – Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 75 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.16.2 GPIO_MUX2 The eight pins of the GPIO_MUX2 block can be selectively mapped to eight General-Purpose Inputs, eight General-Purpose Outputs, or six COMPOUT outputs from the Analog Comparator peripheral. Each GPIO_MUX2 pin can have a pullup enabled or disabled. On reset, all pins of the GPIO_MUX2 block are configured as analog inputs, and the GPIO function is disabled. The GPIO_MUX2 block is programmed through a separate set of registers from those used to program GPIO_MUX1. The multiple registers responsible for configuring the GPIO_MUX2 pins are organized in register set G. They are accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU only. The middle portion of Figure 3-17 shows set G of Control Subsystem registers, plus muxing logic for the associated eight GPIO pins. The GPGMUX1 register selects one of six possible digital output signals from analog comparators, or one of eight general-purpose GPIO digital outputs. The GPGPUD register disables pullups for the GPIO_MUX2 pins when a corresponding bit of that register is set to "1". Other registers of set G allow reading and writing of the eight GPIO bits, as well as setting the direction for each of the bits (read or write). See Table 3-31 for the mapping of comparator outputs and GPIO to the eight pins of GPIO_MUX2. Peripheral Modes 0, 1, 2, and 3 are chosen by setting selected bit pairs of GPGMUX1 register to "00", "01", "10", and "11", respectively. For example, setting bits 5–4 of the GPGMUX1 register to "00" (Peripheral Mode 0) assigns pin GPIO130 to internal signal GPIO130 (digital GPIO). Setting bits 5–4 of the GPGMUX1 register to "11" (Peripheral Mode 3) assigns pin GPIO130 to internal signal COMP6OUT coming from Analog Comparator 6. Peripheral Modes 1 and 2 are reserved and are not currently available. Table 3-31. GPIO_MUX2 Pin Assignments (Cf20;BACKGROUND-COLOR:#4ae2f7">28x Peripheral Modes)(1) Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cf20;BACKGROUND-COLOR:#4ae2f7">28x Device Pin Name Peripheral Peripheral Peripheral Peripheral Mode 0 Mode 1 Mode 2 Mode 3 GPIO1f20;BACKGROUND-COLOR:#4ae2f7">28 GPIO1f20;BACKGROUND-COLOR:#4ae2f7">28 – – – GPIO129 GPIO129 – – COMP1OUT GPIO130 GPIO130 – – COMP6OUT GPIO131 GPIO131 – – COMP2OUT GPIO132 GPIO132 – – COMP3OUT GPIO133 GPIO133 – – COMP4OUT GPIO134 GPIO134 – – – GPIO135 GPIO135 – – COMP5OUT (1) Blank fields represent Reserved functions. 76 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 3-17. Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2 Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 77 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.16.3 AIO_MUX1 The ten pins of AIO_MUX1 can be selectively mapped through a dedicated set of registers to 12 analog inputs for ADC1 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or four General-Purpose Outputs. Note that while AIO_MUX1 has been named after the analog signals passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the AIO_MUX1 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX1 block is programmed through a separate set of registers from those used to program AIO_MUX2. The multiple registers responsible for configuring the AIO_MUX1 pins are accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU only. The top portion of Figure 3-17 shows Control Subsystem registers and muxing logic for the associated ten AIO pins. The AIOMUX1 register selects one of ten possible analog input signals or one of four general-purpose AIO inputs. Other registers allow reading and writing of the four AIO bits, as well as setting the direction for each of the bits (read or write). See Table 3-32 for the mapping of analog inputs and AIOs to the ten pins of AIO_MUX1. AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX1 register to '0'. AIO Mode 1 is chosen by setting selected odd bits of the AIOMUX1 register to '1'. For example, setting bit 5 of the AIOMUX1 register to '0' assigns pin ADC1INA2 to internal signal AIO2 (digital GPIO). Setting bit 5 of the AIOMUX1 register to '1' assigns pin ADC1INA2 to analog inputs ADC1INA2 or COMPA1 (only one should be enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX1 register are "don't cares". Table 3-32. AIO_MUX1 Pin Assignments (Cf20;BACKGROUND-COLOR:#4ae2f7">28x AIO Modes)(1)(2) Device Pin Name Cf20;BACKGROUND-COLOR:#4ae2f7">28x AIO Mode 0(3) Cf20;BACKGROUND-COLOR:#4ae2f7">28x AIO Mode 1(4) ADC1INA0 – ADC1INA0 ADC1INA2 AIO2 ADC1INA2, COMPA1 ADC1INA3 – ADC1INA3 ADC1INA4 AIO4 ADC1INA4, COMPA2 ADC1INA6 AIO6 ADC1INA6, COMPA3 ADC1INA7 – ADC1INA7 ADC1INB0 – ADC1INB0 ADC1INB3 – ADC1INB3 ADC1INB4 AIO12 ADC1INB4, COMPB2 ADC1INB7 – ADC1INB7 (1) Blank fields represent Reserved functions. (2) For each field with two pins (for example, ADC1INA2, COMPA1), only one pin should be enabled at a time; the other pin should be disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs. (3) AIO Mode 0 represents digital general-purpose inputs or outputs. (4) AIO Mode 1 represents analog inputs for ADC1 or the Comparator module. 78 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.16.4 AIO_MUX2 The ten pins of AIO_MUX2 can be selectively mapped through a dedicated set of registers to 12 analog inputs for ADC2 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or four General-Purpose Outputs. Note that while AIO_MUX2 has been named after the analog signals passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the AIO_MUX2 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX2 block is programmed through a separate set of registers from those used to program AIO_MUX1. The multiple registers responsible for configuring the AIO_MUX2 pins are accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU only. The bottom portion of Figure 3-17 shows Control Subsystem registers and muxing logic for the associated ten AIO pins. The AIOMUX2 register selects one of ten possible analog input signals or one of four general-purpose AIO inputs. Other registers allow reading and writing of the four AIO bits, as well as setting the direction for each of the bits (read or write). See Table 3-33 for the mapping of analog inputs and AIOs to the ten pins of AIO_MUX2. Peripheral Modes 1 and 2 are currently not available. AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX2 register to '0'. AIO Mode 1 is chosen by setting selected odd bits of the AIOMUX2 register to '1'. For example, setting bit 9 of the AIOMUX2 register to '0' assigns pin ADC2INA4 to internal signal AIO20 (digital GPIO). Setting bit 9 of the AIOMUX2 register to '1' assigns pin ADC2INA4 to analog inputs ADC2INA4 or COMPA5 (only one should be enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX2 register are "don't cares". Table 3-33. AIO_MUX2 Pin Assignments (Cf20;BACKGROUND-COLOR:#4ae2f7">28x AIO Modes)(1)(2) Device Pin Name Cf20;BACKGROUND-COLOR:#4ae2f7">28x AIO Mode 0(3) Cf20;BACKGROUND-COLOR:#4ae2f7">28x AIO Mode 1(4) ADC2INA0 – ADC2INA0 ADC2INA2 AIO18 ADC2INA2, COMPA4 ADC2INA3 – ADC2INA3 ADC2INA4 AIO20 ADC2INA4, COMPA5 ADC2INA6 AIO22 ADC2INA6, COMPA6 ADC2INA7 – ADC2INA7 ADC2INB0 – ADC2INB0 ADC2INB3 – ADC2INB3 ADC2INB4 AIOf20;BACKGROUND-COLOR:#4ae2f7">28 ADC2INB4, COMPB5 ADC2INB7 – ADC2INB7 (1) Blank fields represent Reserved functions. (2) For each field with two pins (for example, ADC2INA6, COMPA6), only one pin should be enabled at a time; the other pin should be disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs. (3) AIO Mode 0 represents digital general-purpose inputs or outputs. (4) AIO Mode 1 represents analog inputs for ADC2 or the Comparator module. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 79 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.17 Emulation/JTAG Concerto devices have two types of emulation ports to support debug operations: the 7-pin TI JTAG port and the 5-pin Cortex-M3 Instrumentation Trace Macrocell (ITM) port. The 7-pin TI JTAG port can be used to connect to debug tools via the TI 14-pin JTAG header or the TI 20-pin JTAG header. The 5-pin Cortex- M3 ITM port can only be accessed through the TI 20-pin JTAG header. The JTAG port has seven dedicated pins: TRST, TMS, TDI, TDO, TCK, EMU0, and EMU1. The TRST signal should always be pulled down via a 2.2-kΩ pulldown resistor on the board. EMU0 and EMU1 signals should be pulled up through a pair of pullups ranging from 2.2 kΩ to 4.7 kΩ (depending on the drive strength of the debugger ports). The JTAG port is TI's standard debug port. The ITM port uses five GPIO pins that can be mapped to internal Cortex-M3 ITM trace signals: TRACE0, TRACE1, TRACE2, TRACE3, and TRACECLK. This port is typically used for advanced software debug. TI emulators, and those from other manufacturers, can connect to Concerto devices via TI's 14-pin JTAG header or 20-pin JTAG header. See Figure 3-18 to see how the 14-pin JTAG header connects to Concerto's JTAG port signals. Note that the 14-pin header does not support the ITM debug mode. Figure 3-19 shows two possible ways to connect the 20-pin header to Concerto's emulation pins. The left side of the drawing shows all seven JTAG signals connecting to the 20-pin header similar to the way the 14-pin header was connected. Note that the JTAG EMU0 and EMU1 signals are mapped to the corresponding terminals on the 20-pin header. In this mode, header terminals EMU2, EMU3, and EMU4 are left unconnected and the ITM trace mode is not available. The right side of the drawing shows the same 20-pin header now connected to five ITM signals and five of seven JTAG signals. Note that Concerto's EMU0 and EMU1 signals are left unconnected in this mode; thus, the emulation functions associated with these two signals are not available when debugging with ITM trace. 80 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 A. The GPIO pins (GPIO32–GPIO35 and GPIO43) may be used in the application if ITM trace is not used. Figure 3-18. Connecting to TI 14-Pin JTAG Emulator Header Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 81 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn A. The GPIO pins (GPIO32–GPIO35 and GPIO43) may be used in the application if ITM trace is not used. Figure 3-19. Connecting to TI 20-Pin JTAG Emulator Header 82 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.18 Code Security Module The Code Security Module (CSM) is a security feature incorporated in Concerto devices. The CSM prevents access and visibility to on-chip secure memories by unauthorized persons—that is, the CSM prevents duplication and reverse-engineering of proprietary code. The word "secure" means that access to on-chip secure memories is protected. The word "unsecure" means that access to on-chip secure memory is not protected—that is, the contents of the memory could be read by any means [for example, by using a debugging tool such as Code Composer Studio? Integrated Development Environment (IDE)]. 3.18.1 Functional Description The security module restricts the CPU access to on-chip secure memory without interrupting or stalling CPU execution. When a read occurs to a protected memory location, the read returns a zero value and CPU execution continues with the next instruction. This process, in effect, blocks read and write access to various memories through the JTAG port or external peripherals. Security is defined with respect to the access of on-chip secure memories and prevents unauthorized copying of proprietary code or data. The zone is secure when CPU access to the on-chip secure memories associated with that zone is restricted. When secure, two levels of protection are possible, depending on where the program counter is currently pointing. If code is currently running from inside secure memory, only an access through JTAG is blocked (that is, through the emulator). This process allows secure code to access secure data. Conversely, if code is running from unsecure memory, all accesses to secure memories are blocked. User code can dynamically jump in and out of secure memory, thereby allowing secure function calls from unsecure memory. Similarly, interrupt service routines can be placed in secure memory, even if the main program loop is run from unsecure memory. The code security mechanism present in this device offers dual-zone security for the Cortex-M3 code and single-zone security for the Cf20;BACKGROUND-COLOR:#4ae2f7">28x code. In case of dual-zone security on the master subsystem, the different secure memories (RAMs and flash sectors) can be assigned to different security zones by configuring the GRABRAM and GRABSECT registers associated with each zone. Flash Sector N and Flash Sector A are dedicated to Zone1 and Zone2, respectively, and cannot be allocated to any other zone by configuration. Similarly, flash sectors get assigned to different zones based on the setting in the GRABSECT registers. Security is provided by a CSM password of 1f20;BACKGROUND-COLOR:#4ae2f7">28 bits of data (four 32-bit words) that is used to secure or unsecure the zones. Each zone has its own 1f20;BACKGROUND-COLOR:#4ae2f7">28-bit CSM password. The zone can be unsecured by executing the password match flow (PMF). The CSM password for each zone is stored in its dedicated flash sector. The password storage locations in the flash sector store the CSM password. The password is selected by the system designer. If the password locations of a zone have all 1f20;BACKGROUND-COLOR:#4ae2f7">28 bits as ones, the zone is considered "unsecure". Since new flash devices have erased flash (all ones), only a read of the password locations is required to bring any zone into unsecure mode. If the password locations of a zone have all 1f20;BACKGROUND-COLOR:#4ae2f7">28 bits as zeros, the zone is considered "secure", regardless of the contents of the CSMKEY registers. The user should not use all zeros as a password or reset the device during an erase of the flash. Resetting the device during an erase routine can result in either an all-zero or unknown password. If a device is reset when the password locations are all zeros, the device cannot be unlocked by the password match flow. Using a password of all zeros will seriously limit the user's ability to debug secure code or reprogram the flash. NOTE If a device is reset while the password locations of a zone contain all zeros or an unknown value, that zone will be permanently locked unless a method to run the flash erase routine from secure SARAM is embedded into the flash or OTP. Care must be taken when implementing this procedure to avoid introducing a security hole. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 83 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 3.19 ?CRC Module The ?CRC module is part of the master subsystem. This module can be used by Cortex-M3 software to compute CRC on data and program, which are stored at memory locations that are addressable by Cortex-M3. On this device, the Cortex-M3 Flash Bank and ROM are mapped to the code space that is only accessed by the ICODE/DCODE bus of Cortex-M3; and RAMs are mapped on the SRAM space that is accessible by the SYSTEM bus. Hence, the ?CRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and program. 3.19.1 Functional Description The ?CRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and program. To allow interrupts execution in between CRC calculations for a block of data and to discard the Cortex-M3 literal pool accesses in between executions of the program (which reads data for CRC calculation), the Cortex-M3 ROM, Flash, and RAMs are mapped to a mirrored memory location. The ?CRC module grabs data from the bus to calculate CRC only if the address of the read data belongs to mirrored memory space. After grabbing, the ?CRC module performs the CRC calculation on the grabbed data and updates the ?CRC Result Register (?CRCRES). This register can be read at any time to get the calculated CRC for all the previous read data. The ?CRC module only supports CRC calculation for byte accesses. So, in order to calculate the CRC on a block of data, software must perform byte accesses to all the data. For half-word and word accesses, the ?CRC module discards the data and does not update the ?CRCRES register. NOTE If a read to a mirrored address space is thrown from the debugger (Code Composer Studio or any other debug platform), the ?CRC module ignores the read data and does not update the CRC result for that particular read. 3.19.2 CRC Polynomials The following are the CRC polynomials that are supported by the ?CRC module: ? CRC8 Polynomial = 0x07 ? CRC16 Polynomial-1 = 0x8005 ? CRC16 Polynomial-2 = 0x1021 ? CRC32 Polynomial = 0x04C11DB7 3.19.3 CRC Calculation Procedure The software procedure for calculating CRC for a set of data that is stored in Cortex-M3 addressable memory space is as follows: 1. Save the current value of the ?CRC Result Register (?CRCRES) into the stack to allow calculation of CRC in nested interrupt 2. Clear the ?CRC Result Register (?CRCRES) by setting the CLEAR field of the ?CRC Control Register (?CRCCONTROL) to "1" 3. Configure the ?CRC polynomials (CRC8, CRC16-P1, CRC16-P2, or CRC32) in the ?CRC Configuration Register (?CRCCONFIG) 4. Read the data from memory locations for which CRC needs to be calculated using mirrored address 5. Read the ?CRCRES register to get the calculated CRC value. Pop the last saved value of the CRC from the stack and store this value into the ?CRC Result Register (uCRCRES) 84 Device Overview Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 3.19.4 CRC Calculation for Data Stored In Secure Memory This device has dual-zone security for the Cortex-M3 subsystem. Since ZoneX (X → 1/2) software does not have access to program/data in ZoneY (Y → 2/1), code running from ZoneX cannot calculate CRC on data stored in ZoneY memory. Similarly, in the case of Exe-Only flash sectors, even though software is running from same secure zone, the software cannot read the data stored in Exe-Only sectors. However, hardware does allow CRC computation on data stored in Exe-Only flash sectors as long as the read access for this data is initiated by code running from same secure zone. These reads are just dummy reads and, in this case, read data only goes to the ?CRC module, not to the CPU. Copyright ? 2011–2014, Texas Instruments Incorporated Device Overview 85 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 4 Terminal Description 4.1 Terminal Assignments Figure 4-1 shows the 144-pin RFP PowerPAD Thermally Enhanced Thin Quad Flatpack pin assignments. A. All I/Os, except for GPIO135, are glitch-free during power up and power down. See Section 3.11. B. See Table 4-1, Terminal Functions, for the complete multiplexed signal names. Figure 4-1. 144-Pin RFP PowerPAD Thermally Enhanced Thin Quad Flatpack (Top View) 86 Terminal Description Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 4.2 Terminal Functions Table 4-1 describes the signals. Table 4-1. Terminal Functions(1) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. ADC 1 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 1 ADC1 External High Reference – used only when ADC1VREFHI 120 I in ADC external reference mode. ADC1 External Low Reference – used only when ADC1VREFLO see VSSA1 I in ADC external reference mode. ADC1INA0 121 I ADC1 Group A, Channel 0 input ADC1INA2 I ADC1 Group A, Channel 2 input COMPA1 122 I Comparator Input A1 4 mA AIO2 I/O Digital AIO2 ADC1INA3 123 I ADC1 Group A, Channel 3 input ADC1INA4 I ADC1 Group A, Channel 4 input COMPA2 124 I Comparator Input A2 4 mA AIO4 I/O Digital AIO4 ADC1INA6 I ADC1 Group A, Channel 6 input COMPA3 125 I Comparator Input A3 4 mA AIO6 I/O Digital AIO6 ADC1INA7 126 I ADC1 Group A, Channel 7 input ADC1INB0 117 I ADC1 Group B, Channel 0 input ADC1INB3 116 I ADC1 Group B, Channel 3 input ADC1INB4 I ADC1 Group B, Channel 4 input COMPB2 115 I Comparator Input B2 4 mA AIO12 I/O Digital AIO12 ADC1INB7 114 I ADC1 Group B, Channel 7 input ADC 2 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 2 ADC2 External High Reference – used only when ADC2VREFHI 133 I in ADC external reference mode. ADC2 External Low Reference – used only when ADC2VREFLO see VSSA2 I in ADC external reference mode. ADC2INA0 132 I ADC2 Group A, Channel 0 input ADC2INA2 I ADC2 Group A, Channel 2 input COMPA4 131 I Comparator Input A4 4 mA AIO18 I/O Digital AIO18 ADC2INA3 130 I ADC2 Group A, Channel 3 input ADC2INA4 I ADC2 Group A, Channel 4 input COMPA5 129 I Comparator Input A5 4 mA AIO20 I/O Digital AIO20 ADC2INA6 I ADC2 Group A, Channel 6 input COMPA6 1f20;BACKGROUND-COLOR:#4ae2f7">28 I Comparator Input A6 4 mA AIO22 I/O Digital AIO22 ADC2INA7 127 I ADC2 Group A, Channel 7 input ADC2INB0 136 I ADC2 Group B, Channel 0 input ADC2INB3 137 I ADC2 Group B, Channel 3 input Copyright ? 2011–2014, Texas Instruments Incorporated Terminal Description 87 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. ADC2INB4 I ADC2 Group B, Channel 4 input COMPB5 138 I Comparator Input B5 4 mA AIOf20;BACKGROUND-COLOR:#4ae2f7">28 I/O Digital AIOf20;BACKGROUND-COLOR:#4ae2f7">28 ADC2INB7 139 I ADC2 Group B, Channel 7 input ADC Modules Analog Power and Ground 3.3-V Analog Module 1 Power Pin. Tie with VDDA1 119 a 2.2-?F capacitor (typical) close to the pin. 3.3-V Analog Module 2 Power Pin. Tie with VDDA2 134 a 2.2-?F capacitor (typical) close to the pin. Analog ground for ADC1, ADC1VREFLO, VSSA1 118 COMP1–3, and DAC1–3 Analog ground for ADC2, ADC2VREFLO, VSSA2 135 COMP4–6, and DAC4–6 Analog Comparator Results (Digital) and GPIO Group 2 (Cf20;BACKGROUND-COLOR:#4ae2f7">28x Access Only) GPIO1f20;BACKGROUND-COLOR:#4ae2f7">28 140 I/O General-purpose input/output 1f20;BACKGROUND-COLOR:#4ae2f7">28 PU 4 mA GPIO129 I/O General-purpose input/output 129 141 PU 4 mA COMP1OUT O Compare result from Analog Comparator 1 GPIO130 I/O General-purpose input/output 130 142 PU 4 mA COMP6OUT O Compare result from Analog Comparator 6 GPIO131 I/O General-purpose input/output 131 143 PU 4 mA COMP2OUT O Compare result from Analog Comparator 2 GPIO132 I/O General-purpose input/output 132 112 PU 8 mA COMP3OUT O Compare result from Analog Comparator 3 GPIO133 I/O General-purpose input/output 133 111 PU 4 mA COMP4OUT O Compare result from Analog Comparator 4 GPIO134 110 I/O General-purpose input/output 134 PU 4 mA GPIO135(4) I/O General-purpose input/output 135 109 PU 8 mA COMP5OUT O Compare result from Analog Comparator 5 88 Terminal Description Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. GPIO Group 1 and Peripheral Signals PA0_GPIO0 I/O/Z General-purpose input/output 0 M_U0RX I UART-0 receive data M_I2C1SCL 5 I/OD I2C-1 clock open-drain bidirectional port PU 4 mA M_U1RX I UART-1 receive data C_EPWM1A O Enhanced PWM-1 output A PA1_GPIO1 I/O/Z General-purpose input/output 1 M_U0TX O UART-0 transmit data M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port M_U1TX 6 O UART-1 data transmit PU 4 mA M_SSI1FSS I/O SSI-1 frame C_EPWM1B O Enhanced PWM-1 output B C_ECAP6 I/O Enhanced Capture-6 input/output PA2_GPIO2 I/O/Z General-purpose input/output 2 M_SSI0CLK I/O SSI-0 clock 7 PU 4 mA M_MIITXD2 O EMAC MII transmit data bit 2 C_EPWM2A O Enhanced PWM-2 output A PA3_GPIO3 I/O/Z General-purpose input/output 3 M_SSI0FSS I/O SSI-0 frame M_MIITXD1 O EMAC MII transmit data bit 1 8 PU 4 mA M_SSI1CLK I/O SSI-1 clock C_EPWM2B O Enhanced PWM-2 output B C_ECAP5 I/O Enhanced Capture-5 input/output PA4_GPIO4 I/O/Z General-purpose input/output 4 M_SSI0RX I SSI-0 receive data M_MIITXD0 9 O EMAC MII transmit data bit 0 PU 4 mA M_CAN0RX I CAN-0 receive data C_EPWM3A O Enhanced PWM-3 output A PA5_GPIO5 I/O/Z General-purpose input/output 5 M_SSI0TX O SSI-0 transmit data M_MIIRXDV I EMAC MII receive data valid M_CAN0TX 12 O CAN-0 transmit data PU 4 mA C_EPWM3B O Enhanced PWM-3 output B C_MFSRA I McBSP-A receive frame sync C_ECAP1 I/O Enhanced Capture-1 input/output PA6_GPIO6 I/O/Z General-purpose input/output 6 M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port Capture/Compare/PWM-1 M_CCP1 I/O (General-purpose Timer) M_MIIRXCK I EMAC MII receive clock M_CAN0RX 13 I CAN-0 receive data PU 4 mA USB-0 external power enable M_USB0EPEN O (optionally used in host mode) M_MIITXD3 O EMAC MII transmit data bit 3 C_EPWM4A O Enhanced PWM-4 output A C_EPWMSYNCO O Enhanced PWM-4 external sync pulse Copyright ? 2011–2014, Texas Instruments Incorporated Terminal Description 89 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. PA7_GPIO7 I/O/Z General-purpose input/output 7 M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port Capture/Compare/PWM-4 M_CCP4 I/O (General-purpose Timer) M_MIIRXER I EMAC MII receive error M_CAN0TX O CAN-0 transmit data Capture/Compare/PWM-3 M_CCP3 14 I/O PU 4 mA (General-purpose Timer) USB-0 external power error state M_USB0PFLT I (optionally used in the host mode) M_MIIRXD1 I EMAC MII receive data 1 C_EPWM4B O Enhanced PWM-4 output B C_MCLKRA I McBSP-A receive clock C_ECAP2 I/O Enhanced Capture-1 input/output PB0_GPIO8 I/O/Z General-purpose input/output 8 Capture/Compare/PWM-0 M_CCP0 I/O (General-purpose Timer) M_U1RX I UART-1 data receive data M_SSI2TX O SSI-2 transmit data 15 PU 4 mA M_CAN1TX O CAN-1 transmit data M_U4TX O UART-4 transmit data C_EPWM5A O Enhanced PWM-5 output A C_ADCSOCAO O ADC start-of-conversion A PB1_GPIO9 I/O/Z General-purpose input/output 9 Capture/Compare/PWM-2 M_CCP2 I/O (General-purpose Timer) Capture/Compare/PWM-1 M_CCP1 I/O (General-purpose Timer) 18 PU 4 mA M_U1TX O UART-1 transmit data M_SSI2RX I SSI-2 receive data C_EPWM5B O Enhanced PWM-5 output B C_ECAP3 I/O Enhanced Capture-3 input/output PB2_GPIO10 I/O/Z General-purpose input/output 10 M_I2C0SCL I/OD I2C-0 clock open-drain bidirectional port Capture/Compare/PWM-3 M_CCP3 I/O (General-purpose Timer) Capture/Compare/PWM-0 M_CCP0 I/O (General-purpose Timer) USB-0 external power enable 19 PU 4 mA M_USB0EPEN O (optionally used in the host mode) M_SSI2CLK I/O SSI-2 clock M_CAN1RX I CAN-1 receive data M_U4RX I UART-4 receive data C_EPWM6A O Enhanced PWM-6 output A C_ADCSOCBO O ADC start-of-conversion B 90 Terminal Description Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. PB3_GPIO11 I/O/Z General-purpose input/output 11 M_I2C0SDA I/OD I2C-0 data open-drain bidirectional port USB-0 external power error state M_USB0PFLT I (optionally used in the host mode) 20 PU 4 mA M_SSI2FSS I/O SSI-2 frame M_U1RX I UART-1 receive data C_EPWM6B O Enhanced PWM-6 output B C_ECAP4 I/O Enhanced Capture-4 input/output PB4_GPIO12 I/O/Z General-purpose input/output 12 M_U2RX I UART-2 receive data M_CAN0RX I CAN-0 receive data M_U1RX I UART-1 receive data 30 PU 4 mA M_EPI0S23 I/O EPI-0 signal 23 M_CAN1TX O CAN-1 transmit data M_SSI1TX O SSI-1 transmit data C_EPWM7A O Enhanced PWM-7 output A PB5_GPIO13 I/O/Z General-purpose input/output 13 Capture/Compare/PWM-5 M_CCP5 I/O (General-purpose Timer) Capture/Compare/PWM-6 M_CCP6 I/O (General-purpose Timer) Capture/Compare/PWM-0 M_CCP0 I/O (General-purpose Timer) M_CAN0TX O CAN-0 transmit data 31 PU 4 mA Capture/Compare/PWM-2 M_CCP2 I/O (General-purpose Timer) M_U1TX O UART-1 transmit data M_EPI0S22 I/O EPI-0 signal 22 M_CAN1RX I CAN-1 receive data M_SSI1RX I SSI-1 receive data C_EPWM7B O Enhanced PWM-7 output B PB6_GPIO14 I/O/Z General-purpose input/output 14 Capture/Compare/PWM-1 M_CCP1 I/O (General-purpose Timer) Capture/Compare/PWM-7 M_CCP7 I/O (General-purpose Timer) Capture/Compare/PWM-5 M_CCP5 I/O (General-purpose Timer) 26 PU 4 mA M_EPI0S37(5) I/O EPI-0 signal 37 M_MIICRS I EMAC MII carrier sense M_I2C0SDA I/OD I2C-0 data open-drain bidirectional port M_U1TX O UART-1 transmit data M_SSI1CLK I/O SSI-1 clock C_EPWM8A O Enhanced PWM-8 output A Copyright ? 2011–2014, Texas Instruments Incorporated Terminal Description 91 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. PB7_GPIO15 I/O/Z General-purpose input/output 15 M_EXTNMI I Cortex-M3 external non-maskable interrupt M_MIIRXD1 I EMAC MII receive data 1 M_EPI0S36(5) I/O EPI-0 signal 36 27 PU 4 mA M_I2C0SCL I/OD I2C-0 clock open-drain bidirectional port M_U1RX I UART-1 receive data M_SSI1FSS I/O SSI-1 frame C_EPWM8B O Enhanced PWM-8 output B PD0_GPIO16 I/O/Z General-purpose input/output 16 M_CAN0RX I CAN-0 receive data M_U2RX I UART-2 receive data M_U1RX I UART-1 receive data Capture/Compare/PWM-6 M_CCP6 I/O (General-purpose Timer) M_MIIRXDV 102 I EMAC MII receive data valid PU 4 mA M_MIIRXD2 I EMAC MII receive data 2 M_SSI0TX O SSI-0 transmit data M_CAN1TX O CAN-1 transmit data USB-0 external power enable M_USB0EPEN O (optionally used in the host mode) C_SPISIMOA I/O SPI-A slave in, master out PD1_GPIO17 I/O/Z General-purpose input/output 17 M_CAN0TX O CAN-0 transmit data M_U2TX O UART-2 transmit data M_U1TX O UART-1 transmit data Capture/Compare/PWM-7 M_CCP7 I/O (General-purpose Timer) M_MIITXER O EMAC MII transmit error 98 PU 4 mA Capture/Compare/PWM-2 M_CCP2 I/O (General-purpose Timer) M_MIICOL I EMAC MII collision detect M_SSI0RX I SSI-0 receive data M_CAN1RX I CAN-1 receive data USB-0 external power error state M_USB0PFLT I (optionally used in the host mode) C_SPISOMIA I/O SPI-A master in, slave out PD2_GPIO18 I/O/Z General-purpose input/output 18 M_U1RX I UART-1 receive data Capture/Compare/PWM-6 M_CCP6 I/O (General-purpose Timer) Capture/Compare/PWM-5 M_CCP5 I/O (General-purpose Timer) f20;BACKGROUND-COLOR:#4ae2f7">28 PU 4 mA M_EPI0S20 I/O EPI-0 signal 20 M_SSI0CLK I/O SSI-0 clock M_U1TX O UART-1 transmit data M_CAN0RX I CAN-0 receive data C_SPICLKA I/O SPI-A clock 92 Terminal Description Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. PD3_GPIO19 I/O/Z General-purpose input/output 19 M_U1TX O UART-1 transmit data Capture/Compare/PWM-7 M_CCP7 I/O (General-purpose Timer) Capture/Compare/PWM-0 M_CCP0 I/O (General-purpose Timer) 29 PU 4 mA M_EPI0S21 I/O EPI-0 signal 21 M_SSI0FSS I/O SSI-0 frame M_U1RX I UART-1 receive data M_CAN0TX O CAN-0 transmit data C_SPISTEA I/O SPI-A slave transmit enable PD4_GPIO20 I/O/Z General-purpose input/output 20 Capture/Compare/PWM-0 M_CCP0 I/O (General-purpose Timer) Capture/Compare/PWM-3 M_CCP3 I/O (General-purpose Timer) M_MIITXD3 O EMAC MII transmit data 3 65 PU 4 mA M_EPI0S19 I/O EPI-0 signal 19 M_U3TX O UART-3 transmit data M_CAN1TX O CAN-1 transmit data C_EQEP1A I Enhanced QEP-1 input A C_MDXA O McBSP-A transmit data PD5_GPIO21 I/O/Z General-purpose input/output 21 Capture/Compare/PWM-2 M_CCP2 I/O (General-purpose Timer) Capture/Compare/PWM-4 M_CCP4 I/O (General-purpose Timer) M_MIITXD2 O EMAC MII transmit data 2 64 PU 6 mA M_U2RX I UART-2 receive data M_EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 I/O EPI-0 signal f20;BACKGROUND-COLOR:#4ae2f7">28 M_U3RX I UART-3 receive data M_CAN1RX I CAN-1 receive data C_EQEP1B I Enhanced QEP-1 input B C_MDRA I McBSP-A receive data PD6_GPIO22 I/O/Z General-purpose input/output 22 M_MIITXD1 O EMAC MII transmit data 1 M_U2TX O UART-2 transmit data M_EPI0S29 I/O EPI-0 signal 29 73 PU 6 mA M_I2C1SDA I/OD I2C-0 data open-drain bidirectional port M_U1TX O UART-1 transmit data C_EQEP1S I/O Enhanced QEP-1 strobe C_MCLKXA O McBSP-A transmit clock Copyright ? 2011–2014, Texas Instruments Incorporated Terminal Description 93 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. PD7_GPIO23 I/O/Z General-purpose input/output 23 Capture/Compare/PWM-1 M_CCP1 I/O (General-purpose Timer) M_MIITXD0 O EMAC MII transmit data 0 M_EPI0S30 I/O EPI-0 signal 30 68 PU 6 mA M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port M_U1RX I UART-1 receive data C_EQEP1I I/O Enhanced QEP-1 index C_MFSXA O McBSP-A transmit frame sync PE0_GPIO24 I/O/Z General-purpose input/output 24 M_SSI1CLK I/O SSI-1 clock Capture/Compare/PWM-3 M_CCP3 I/O (General-purpose Timer) M_EPI0S8 I/O EPI-0 signal 8 USB-0 external power error state M_USB0PFLT I 43 PU 4 mA (optionally used in the host mode) M_SSI3TX O SSI-3 transmit data M_CAN0RX I CAN-1 receive data M_SSI1TX O SSI-1 transmit data C_ECAP1 I/O Enhanced Capture-1 input/output C_EQEP2A I Enhanced QEP-2 input A PE1_GPIO25 I/O/Z General-purpose input/output 25 M_SSI1FSS I/O SSI-1 frame Capture/Compare/PWM-2 M_CCP2 I/O (General-purpose Timer) Capture/Compare/PWM-6 M_CCP6 I/O (General-purpose Timer) 45 PU 4 mA M_EPI0S9 I/O EPI-0 signal 9 M_SSI3RX I SSI-3 receive data M_CAN0TX O CAN-1 transmit data M_SSI1RX O SSI-1 receive data C_ECAP2 I/O Enhanced Capture-2 input/output C_EQEP2B I Enhanced QEP-2 input B PE2_GPIO26 I/O/Z General-purpose input/output 26 Capture/Compare/PWM-4 M_CCP4 I/O (General-purpose Timer) M_SSI1RX I SSI-1 receive data Capture/Compare/PWM-2 M_CCP2 I/O (General-purpose Timer) 32 PU 4 mA M_EPI0S24 I/O EPI-0 signal 24 M_SSI3CLK I/O SSI-3 clock M_U2RX I UART-2 receive data M_SSI1CLK I/O SSI-1 clock C_ECAP3 I/O Enhanced Capture-3 input/output C_EQEP2I I/O Enhanced QEP-2 index 94 Terminal Description Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. PE3_GPIO27 I/O/Z General-purpose input/output 27 Capture/Compare/PWM-1 M_CCP1 I/O (General-purpose Timer) M_SSI1TX O SSI-1 transmit data Capture/Compare/PWM-7 M_CCP7 I/O (General-purpose Timer) 33 PU 4 mA M_EPI0S25 I/O EPI-0 signal 25 M_SSI3FSS I/O SSI-3 frame M_U2TX O UART-2 transmit data M_SSI1FSS I/O SSI-1 frame C_ECAP4 I/O Enhanced Capture-4 input/output C_EQEP2S I/O Enhanced QEP-2 strobe PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 I/O/Z General-purpose input/output f20;BACKGROUND-COLOR:#4ae2f7">28 Capture/Compare/PWM-3 M_CCP3 I/O (General-purpose Timer) M_U2TX O UART-2 transmit data Capture/Compare/PWM-2 M_CCP2 I/O (General-purpose Timer) M_MIIRXD0 I EMAC MII receive data 0 77 PU 4 mA M_EPI0S34(5) I/O EPI-0 signal 34 M_U0RX I UART-0 receive data M_EPI0S38(5) I/O EPI-0 signal 38 USB-0 external power enable M_USB0EPEN O (optionally used in the host mode) C_SCIRXDA I SCI-A receive data PE5_GPIO29 I/O/Z General-purpose input/output 29 Capture/Compare/PWM-5 M_CCP5 I/O (General-purpose Timer) M_EPI0S35(5) I/O EPI-0 signal 35 M_MIITXER 76 O EMAC MII transmit error PU 4 mA M_U0TX O UART-0 transmit data USB-0 external power error state M_USB0PFLT I (optionally used in the host mode) C_SCITXDA O SCI-A transmit data PE6_GPIO30 I/O/Z General-purpose input/output 30 M_MIIMDIO I/O EMAC management data input/output 22 PU 4 mA M_CAN0RX I CAN-0 receive data C_EPWM9A O Enhanced PWM-9 output A PE7_GPIO31 I/O/Z General-purpose input/output 31 M_MIIRXD3 I EMAC MII receive data 3 23 PU 4 mA M_CAN0TX O CAN-0 transmit data C_EPWM9B O Enhanced PWM-9 output B Copyright ? 2011–2014, Texas Instruments Incorporated Terminal Description 95 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. PF0_GPIO32 I/O/Z General-purpose input/output 32 M_CAN1RX I CAN-1 receive data M_MIIRXCK I EMAC MII receive clock M_I2C0SDA I/OD I2C-0 data open-drain bidirectional port 104 PU 4 mA M_TRACED2 O Trace data 2 C_I2CASDA I/OD I2C-A data open-drain bidirectional port C_SCIRXDA I SCI-A receive data C_ADCSOCAO O ADC start-of-conversion A(6) PF1_GPIO33 I/O/Z General-purpose input/output 33 M_CAN1TX O CAN-1 transmit data M_MIIRXER I EMAC MII receive error Capture/Compare/PWM-3 M_CCP3 I/O (General-purpose Timer) 103 PU 4 mA M_I2C0SCL I/OD I2C-0 clock open-drain bidirectional port M_TRACED3 O Trace data 3 C_I2CASCL I/OD I2C-A clock open-drain bidirectional port C_EPWMSYNCO O Enhanced PWM sync out C_ADCSOCBO O ADC start-of-conversion B(6) PF2_GPIO34 I/O/Z General-purpose input/output 34 M_MIIPHYINTR I EMAC PHY MII interrupt M_EPI0S32(5) I/O EPI-0 signal 32 M_SSI1CLK I/O SSI-1 clock M_TRACECLK O Trace clock 82 PU 4 mA M_XCLKOUT O External output clock C_ECAP1 I/O Enhanced Capture-1 input/output C_SCIRXDA I SCI-A receive data C_XCLKOUT O External output clock BOOT_3 I Boot pin 3 PF3_GPIO35 I/O/Z General-purpose input/output 35 M_MIIMDC I EMAC management data clock M_EPI0S33(5) I/O EPI-0 signal 33 M_SSI1FSS I/O SSI-1 frame 81 PU 4 mA M_U0TX O UART-0 transmit data M_TRACED0 O Trace data 0 C_SCITXDA O SCI-A transmit data BOOT_2 I Boot pin 2 PF4_GPIO36 I/O/Z General-purpose input/output 36 Capture/Compare/PWM-0 M_CCP0 I/O (General-purpose Timer) M_MIIMDIO I/O EMAC management data input/output 48 PU 4 mA M_EPI0S12 I/O EPI-0 signal 12 M_SSI1RX I SSI-1 receive data M_U0RX I UART-0 receive data C_SCIRXDA I SCI-A receive data 96 Terminal Description Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. PF5_GPIO37 I/O/Z General-purpose input/output 37 Capture/Compare/PWM-2 M_CCP2 I/O (General-purpose Timer) M_MIIRXD3 I EMAC MII receive data 3 51 PU 4 mA M_EPI0S15 I/O EPI-0 signal 15 M_SSI1TX O SSI-1 transmit data C_ECAP2 I/O Enhanced Capture-2 input/output General-purpose input/output 38. NOTE: For this pin, only the USB0VBUS function PF6_GPIO38 I/O/Z is available on silicon revision 0 devices (GPIO and the four other functions listed are not available). 69 PU 4 mA M_USB0VBUS Analog USB0 VBUS power (5-V tolerant) Capture/Compare/PWM-1 M_CCP1 I/O (General-purpose Timer) M_MIIRXD2 I EMAC MII receive data 2 M_EPI0S38(5) I/O EPI-0 signal 38 PF7_GPIO39 No Pin No Pin General-purpose input/output 39 is not pinned out. PG0_GPIO40 I/O/Z General-purpose input/output 40 M_U2RX I UART-2 receive data M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port USB-0 external power enable M_USB0EPEN 49 O PU 4 mA (optionally used in the host mode) M_EPI0S13 I/O EPI-0 signal 13 M_MIIRXD2 I EMAC MII receive data 2 M_U4RX I UART-4 receive data PG1_GPIO41 I/O/Z General-purpose input/output 41 M_U2TX O UART-2 transmit data M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port 50 PU 4 mA M_EPI0S14 I/O EPI-0 signal 14 M_MIIRXD1 I EMAC MII receive data 1 M_U4TX O UART-4 transmit data PG2_GPIO42 I/O/Z General-purpose input/output 42 M_USB0DM Analog USB0 data minus 71 PU 4 mA M_MIICOL I EMAC MII collision detect M_EPI0S39(5) I/O EPI-0 signal 39 PG3_GPIO43 I/O/Z General-purpose input/output 43 M_MIICRS I EMAC MII carrier sense M_MIIRXDV 78 I EMAC MII receive data valid PU 4 mA M_TRACED1 O Trace data 1 BOOT_0 I Boot pin 0 PG4_GPIO44 No Pin No Pin General-purpose input/output 44 is not pinned out. PG5_GPIO45 I/O/Z General-purpose input/output 45 M_USB0DP Analog USB0 data plus Capture/Compare/PWM-5 M_CCP5 72 I/O PU 4 mA (General-purpose Timer) M_MIITXEN O EMAC MII transmit enable M_EPI0S40(5) I/O EPI-0 signal 40 Copyright ? 2011–2014, Texas Instruments Incorporated Terminal Description 97 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. General-purpose input/output 46. NOTE: For this pin, only the USB0ID function is PG6_GPIO46 I/O/Z available on silicon revision 0 devices (GPIO and the three other functions listed are not available). 70 PU 4 mA M_USB0ID Analog USB0 ID (5-V tolerant) M_MIITXCK I EMAC MII transmit clock M_EPI0S41(5) I/O EPI-0 signal 41 PG7_GPIO47 I/O/Z General-purpose input/output 47 M_MIITXER O EMAC MII transmit error Capture/Compare/PWM-5 M_CCP5 52 I/O PU 6 mA (General-purpose Timer) M_EPI0S31 I/O EPI-0 signal 31 BOOT_1 I Boot pin 1 PH0_GPIO48 I/O/Z General-purpose input/output 48 Capture/Compare/PWM-6 M_CCP6 I/O (General-purpose Timer) M_MIIPHYRST O EMAC PHY MII reset 41 PU 4 mA M_EPI0S6 I/O EPI-0 signal 6 M_SSI3TX O SSI-3 transmit data C_ECAP5 I/O Enhanced Capture-5 input/output PH1_GPIO49 I/O/Z General-purpose input/output 49 Capture/Compare/PWM-7 M_CCP7 I/O (General-purpose Timer) M_EPI0S7 I/O EPI-0 signal 7 42 PU 4 mA M_MIIRXD0 I EMAC MII receive data 0 M_SSI3RX I SSI-3 receive data C_ECAP6 I/O Enhanced Capture-6 input/output PH2_GPIO50 I/O/Z General-purpose input/output 50 M_EPI0S1 I/O EPI-0 signal 1 M_MIITXD3 36 O EMAC MII transmit data 3 PU 4 mA M_SSI3CLK I/O SSI-3 clock C_EQEP1A I Enhanced QEP-1 input A PH3_GPIO51 I/O/Z General-purpose input/output 51 USB-0 external power enable M_USB0EPEN O (optionally used in the host mode) M_EPI0S0 I/O EPI-0 signal 0 35 PU 4 mA M_MIITXD2 O EMAC MII transmit data 2 M_SSI3FSS I/O SSI-3 frame C_EQEP1B I Enhanced QEP-1 input B PH4_GPIO52 I/O/Z General-purpose input/output 52 USB-0 external power error state M_USB0PFLT I (optionally used in the host mode) M_EPI0S10 I/O EPI-0 signal 10 46 PU 4 mA M_MIITXD1 O EMAC MII transmit data 1 M_SSI1CLK I/O SSI-1 clock M_U3TX O UART-3 transmit data C_EQEP1S I/O Enhanced QEP-1 strobe 98 Terminal Description Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. PH5_GPIO53 I/O/Z General-purpose input/output 53 M_EPI0S11 I/O EPI-0 signal 11 M_MIITXD0 O EMAC MII transmit data 0 47 PU 4 mA M_SSI1FSS I/O SSI-1 frame M_U3RX I UART-3 receive data C_EQEP1I I/O Enhanced QEP-1 index PH6_GPIO54 I/O/Z General-purpose input/output 54 M_EPI0S26 I/O EPI-0 signal 26 M_MIIRXDV I EMAC MII receive data valid M_SSI1RX I SSI-1 receive data 79 PU 4 mA M_MIITXEN O EMAC MII transmit enable M_SSI0TX O SSI-0 transmit data C_SPISIMOA I/O SPI-A slave in, master out C_EQEP3A I Enhanced QEP-1 input A PH7_GPIO55 I/O/Z General-purpose input/output 55 M_MIIRXCK I EMAC MII receive clock M_EPI0S27 I/O EPI-0 signal 27 M_SSI1TX O SSI-1 transmit data 80 PU 4 mA M_MIITXCK I EMAC MII transmit clock M_SSI0RX I SSI-0 receive data C_SPISOMIA I/O SPI-A master in, slave out C_EQEP3B I Enhanced QEP-3 input B PJ0_GPIO56 I/O/Z General-purpose input/output 56 M_MIIRXER I EMAC MII receive error M_EPI0S16 I/O EPI-0 signal 16 M_I2C1SCL 63 I/OD I2C-1 clock open-drain bidirectional port PU 4 mA M_SSI0CLK I/O SSI-0 clock C_SPICLKA I/O SPI-A clock C_EQEP3S I/O Enhanced QEP-3 strobe PJ1_GPIO57 I/O/Z General-purpose input/output 57 M_EPI0S17 I/O EPI-0 signal 17 USB-0 external power error state M_USB0PFLT I (optionally used in the host mode) M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port 62 PU 4 mA M_MIIRXDV I EMAC MII receive data valid M_SSI0FSS I/O SSI-0 frame C_SPISTEA I/O SPI-A slave transmit enable C_EQEP3I I/O Enhanced QEP-3 index Copyright ? 2011–2014, Texas Instruments Incorporated Terminal Description 99 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. PJ2_GPIO58 I/O/Z General-purpose input/output 58 M_EPI0S18 I/O EPI-0 signal 18 Capture/Compare/PWM-0 M_CCP0 I/O (General-purpose Timer) M_MIIRXCK I EMAC MII receive clock 61 PU 4 mA M_SSI0CLK I/O SSI-0 clock M_U0TX O UART-0 transmit data C_MCLKRA I McBSP-A receive clock C_EPWM7A O Enhanced PWM-7 output A PJ3_GPIO59 I/O/Z General-purpose input/output 59 M_EPI0S19 I/O EPI-0 signal 19 Capture/Compare/PWM-6 M_CCP6 I/O (General-purpose Timer) M_MIIMDC O EMAC management data clock 60 PU 4 mA M_SSI0FSS I/O SSI-0 frame M_U0RX I UART-0 receive data C_MFSRA I McBSP-A receive frame sync C_EPWM7B O Enhanced PWM-7 output B PJ4_GPIO60 I/O/Z General-purpose input/output 60 M_EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 I/O EPI-0 signal f20;BACKGROUND-COLOR:#4ae2f7">28 Capture/Compare/PWM-4 M_CCP4 I/O (General-purpose Timer) 57 PU 6 mA M_MIICOL I EMAC MII collision detect M_SSI1CLK I/O SSI-1 clock C_EPWM8A O Enhanced PWM-8 output A PJ5_GPIO61 I/O/Z General-purpose input/output 61 M_EPI0S29 I/O EPI-0 signal 29 Capture/Compare/PWM-2 M_CCP2 I/O (General-purpose Timer) 56 PU 6 mA M_MIICRS I EMAC MII carrier sense M_SSI1FSS I/O SSI-1 frame C_EPWM8B O Enhanced PWM-8 output B PJ6_GPIO62 I/O/Z General-purpose input/output 62 M_EPI0S30 I/O EPI-0 signal 30 Capture/Compare/PWM-1 M_CCP1 I/O (General-purpose Timer) 53 PU 6 mA M_MIIPHYINTR I EMAC PHY MII interrupt M_U2RX I UART-2 receive data C_EPWM9A O Enhanced PWM-9 output A PJ7_GPIO63 I/O/Z General-purpose input/output 63 Capture/Compare/PWM-0 M_CCP0 I/O (General-purpose Timer) 97 PU 4 mA M_MIIPHYRST O EMAC PHY MII reset M_U2TX O UART-2 transmit data C_EPWM9B O Enhanced PWM-9 output B PC0_GPIO64 No Pin No Pin General-purpose input/output 64 is not pinned out. PC1_GPIO65 No Pin No Pin General-purpose input/output 65 is not pinned out. 100 Terminal Description Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. PC2_GPIO66 No Pin No Pin General-purpose input/output 66 is not pinned out. PC3_GPIO67 No Pin No Pin General-purpose input/output 67 is not pinned out. PC4_GPIO68 I/O/Z General-purpose input/output 68 Capture/Compare/PWM-5 M_CCP5 I (General-purpose Timer) M_MIITXD3 O EMAC MII transmit data 3 Capture/Compare/PWM-2 M_CCP2 I 37 (General-purpose Timer) PU 4 mA Capture/Compare/PWM-4 M_CCP4 I (General-purpose Timer) M_EPI0S2 I/O EPI-0 signal 2 Capture/Compare/PWM-1 M_CCP1 I (General-purpose Timer) PC5_GPIO69 I/O/Z General-purpose input/output 69 Capture/Compare/PWM-1 M_CCP1 I (General-purpose Timer) Capture/Compare/PWM-3 M_CCP3 38 I PU 4 mA (General-purpose Timer) USB-0 external power enable M_USB0EPEN O (optionally used in the host mode) M_EPI0S3 I/O EPI-0 signal 3 PC6_GPIO70 I/O/Z General-purpose input/output 70 Capture/Compare/PWM-3 M_CCP3 I (General-purpose Timer) M_U1RX I UART-1 receive data 39 PU 4 mA Capture/Compare/PWM-0 M_CCP0 I (General-purpose Timer) USB-0 external power error state M_USB0PFLT I (optionally used in the host mode) M_EPI0S4 I/O EPI-0 signal 4 PC7_GPIO71 I/O/Z General-purpose input/output 71 Capture/Compare/PWM-4 M_CCP4 I (General-purpose Timer) Capture/Compare/PWM-0 M_CCP0 I (General-purpose Timer) 40 PU 4 mA M_U1TX O UART-1 transmit data USB-0 external power error state M_USB0PFLT I (optionally used in the host mode) M_EPI0S5 I/O EPI-0 signal 5 Copyright ? 2011–2014, Texas Instruments Incorporated Terminal Description 101 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. Resets Digital Subsystem Reset (in) and Watchdog/Power-on Reset (out). In most applications, TI recommends that the XRS pin be tied with the ARS pin. The Digital Subsystem has a built-in POR circuit, and during a power-on condition, this pin is driven low by the Digital Subsystem. This pin is also driven low by the Digital Subsystem when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin to assert device reset. In this case, XRS 4 I/OD PU 4 mA TI recommends that this pin be driven by an open- drain device. An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, a device reset causes the Digital Subsystem to terminate execution. The Cortex-M3 program counter points to the address contained at the location 0x00000004. The Cf20;BACKGROUND-COLOR:#4ae2f7">28 program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. Analog Subsystem Reset (in) and Power-on Reset (out). In most applications, TI recommends that the ARS pin be tied with the XRS pin. The Analog Subsystem has a built-in POR circuit, and during a power-on condition, this pin is driven low by the Analog Subsystem. If need be, an external circuitry may also drive this pin to assert a device ARS 144 I/OD reset. In this case, TI recommends that this pin be PU 4 mA driven by an open-drain device. An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, the Analog Subsystem reset causes the digital logic associated with the Analog Subsystem, to enter reset state. The output buffer of this pin is an open-drain with an internal pullup. 102 Terminal Description Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. Clocks External oscillator input or on-chip crystal- oscillator input. To use the on-chip oscillator, a X1 93 I quartz crystal or a ceramic resonator must be connected across X1 and X2. See Figure 3-7. On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X2 95 O X1 and X2. If X2 is not used, it must be left unconnected. See Figure 3-7. Clock Oscillator Ground Pin. Use this pin to connect the GND of external crystal load VSSOSC 94 capacitors or the ground pin of 3-terminal ceramic resonators with built-in capacitors. Do not connect to board ground. See Figure 3-7. External oscillator input. This pin feeds a clock see XCLKIN I from an external 3.3-V oscillator to internal USB PJ7_GPIO63 PLL module and to the CAN peripherals. External oscillator output. This pin outputs a clock see divided-down from the internal PLL System Clock. XCLKOUT O/Z PF2_GPIO34 The divide ratio is defined in the XPLLCLKCFG register. Boot Pins One of four boot mode pins. BOOT_0 selects a see BOOT_0 I specific configuration source from which the PU PG3_GPIO43 Concerto device boots on start-up. One of four boot mode pins. BOOT_1 selects a see BOOT_1 I specific configuration source from which the PU PG7_GPIO47 Concerto device boots on start-up. One of four boot mode pins. BOOT_2 selects a see BOOT_2 I specific configuration source from which the PU PF3_GPIO35 Concerto device boots on start-up. One of four boot mode pins. BOOT_3 selects a see BOOT_3 I specific configuration source from which the PU PF2_GPIO34 Concerto device boots on start-up. JTAG JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active-low test pin and must be maintained low during normal device operation. An external pulldown resistor is TRST 85 I PD required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. TCK 89 I JTAG test clock JTAG test-mode select (TMS) with internal pullup. TMS 87 I This serial control input is clocked into the TAP PU controller on the rising edge of TCK. JTAG test data input (TDI) with internal pullup. TDI 88 I TDI is clocked into the selected register PU (instruction or data) on a rising edge of TCK. Copyright ? 2011–2014, Texas Instruments Incorporated Terminal Description 103 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. JTAG scan out, test data output (TDO). The contents of the selected register (instruction or TDO 84 O 4 mA data) are shifted out of TDO on the falling edge of TCK. Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based EMU0 83 I/O/Z on the drive strength of the debugger pods PU 4 mA applicable to the design. A 2.2-k? to 4.7-k? resistor is generally adequate. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters Wait-in-Reset mode. WIR suspends bootloader execution, allowing the Emulator to connect to the device and to modify FLASH contents. Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based EMU1 86 I/O/Z on the drive strength of the debugger pods PU 4 mA applicable to the design. A 2.2-k? to 4.7-k? resistor is generally adequate. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters Wait-in-Reset mode. WIR suspends bootloader execution, allowing the Emulator to connect to the device and to modify FLASH contents. ITM Trace (ARM Instrumentation Trace Macrocell) see TRACED0 O ITM Trace data 0 4 mA PF3_GPIO35 see TRACED1 O ITM Trace data 1 4 mA PG3_GPIO43 see TRACED2 O ITM Trace data 2 4 mA PF0_GPIO32 see TRACED3 O ITM Trace data 3 4 mA PF1_GPIO33 see TRACECLK O ITM Trace clock 4 mA PF2_GPIO34 104 Terminal Description Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. Test Pins FLASH Test Pin 1. Reserved for TI. Must be left FLT1 16 I/O unconnected. FLASH Test Pin 2. Reserved for TI. Must be left FLT2 21 I/O unconnected. Internal Voltage Regulator Control Internal 1.8-V VREG Enable/Disable for VDD18. VREG18EN 113 Pull low to enable the internal 1.8-V voltage PD regulator (VREG18), pull high to disable VREG18. Internal 1.2-V VREG Enable/Disable for VDD12. VREG12EN 101 Pull low to enable the internal 1.2-V voltage PD regulator (VREG12), pull high to disable VREG12. Digital Logic Power Pins for I/Os, Flash, USB, and Internal Oscillators VDDIO 107 VDDIO 10 VDDIO 25 VDDIO 34 VDDIO 44 VDDIO 54 3.3-V Digital I/O and FLASH Power Pin. Tie with a VDDIO 59 0.1-?F capacitor (typical) close to the pin. When the 1.2-V VREG is enabled (by pulling the VDDIO 105 VREG12EN pin low), these pins also supply VDDIO 3 power to the Digital Subsystem. When the 1.8-V VDDIO 67 VREG is enabled (by pulling the VREG18EN pin low), these pins also supply power to the Analog VDDIO 74 Subsystem. VDDIO 92 VDDIO 100 VDDIO 96 VDDIO 17 VDDIO 2 VDDIO 106 Digital Logic Power Pins (Analog Subsystem) VDD18 1 1.8-V Digital Logic Power Pins (associated with the Analog Subsystem) - no supply needed when using internal VREG18. Tie with 1.2-?F (minimum) ceramic capacitor (10% tolerance) to ground when VDD18 108 using internal VREG. Higher value capacitors may be used but could impact supply-rail ramp-up time. Copyright ? 2011–2014, Texas Instruments Incorporated Terminal Description 105 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 4-1. Terminal Functions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFER RFP NAME PD(3) STRENGTH PIN NO. Digital Logic Power Pins (Master and Control Subsystems) VDD12 24 VDD12 55 1.2-V Digital Logic Power Pins - no supply needed VDD12 66 when using internal VREG12. Tie with 250-nF VDD12 99 (minimum) to 750-nF (maximum) ceramic capacitor (10% tolerance) to ground when using VDD12 75 internal VREG. Higher value capacitors may be VDD12 58 used but could impact supply-rail ramp-up time. VDD12 11 VDD12 90 Digital Logic Ground (Analog, Master, and Control Subsystems) Digital Ground Power Pad (located on the bottom VSS PWR PAD of the chip) No Connect Pins This pin is a "no connect" (that is, this pin is not NC 91 connected to any circuitry internal to the device). (1) Throughout this table, Master Subsystem signals are denoted by the color "blue"; Control Subsystem signals are denoted by the color "green"; and Analog Subsystem signals are denoted by the color "orange". (2) I = Input, O = Output, Z = High Impedance, OD = Open Drain (3) PU = Pullup, PD = Pulldown – GPIO_MUX1 pullups can be enabled or disabled by Cortex-M3 software (disabled on reset). – GPIO_MUX2 pullups can be enabled or disabled by Cf20;BACKGROUND-COLOR:#4ae2f7">28x software (disabled on reset). – AIO_MUX1 and AIO_MUX2 terminals do not have pullups or pulldowns. – All other pullups are always enabled (XRS, ARS, TMS, TDI, EMU0, EMU1). – All pulldowns are always enabled (VREG18EN, VREG12EN, TRST). (4) All I/Os, except for GPIO135, are glitch-free during power up and power down. See Section 3.11. (5) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices. (6) Output from the Concerto ePWM is meant for the external ADC (if present). 106 Terminal Description Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 5 Device Operating Conditions 5.1 Absolute Maximum Ratings(1) (2) Supply voltage range, VDDIO (I/O and Flash) with respect to VSS –0.3 V to 4.6 V Supply voltage range, VDD18 with respect to VSS –0.3 V to 2.5 V Supply voltage range, VDD12 with respect to VSS –0.3 V to 1.5 V Analog voltage range, VDDA with respect to VSSA –0.3 V to 4.6 V Input voltage range, VIN (3.3 V) –0.3 V to 4.6 V Output voltage range, VO –0.3 V to 4.6 V Supply Ramp Rate (VDDIO, VDD18, VDD12, VDDA) with respect to VSS < 105 V/s Input clamp current, IIK (VIN < 0 or VIN > VDDIO)(3) ±20 mA Output clamp current, IOK (VO < 0 or VO > VDDIO) ±20 mA Free-Air temperature, TA –40°C to 125°C Junction temperature range, TJ (4) –40°C to 150°C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VSS, unless otherwise noted. (3) Continuous clamp current per pin is ± 2 mA. (4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320Ff20;BACKGROUND-COLOR:#4ae2f7">28xx Devices Application Report (literature number SPRA963). 5.2 Handling Ratings MIN MAX UNIT Tstg Storage temperature range(1) –65 150 °C VESD (2) Human Body Model (HBM) ESD Stress Voltage(3) –2 2 kV Charged Device Model (CDM) ESD Stress Voltage(4) –500 500 V (1) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320Ff20;BACKGROUND-COLOR:#4ae2f7">28xx Devices Application Report (literature number SPRA963). (2) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into the device. (3) Level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance. (4) Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 250-V CDM is possible if necessary precautions are taken. Pins listed as 250 V may actually have higher performance. Copyright ? 2011–2014, Texas Instruments Incorporated Device Operating Conditions 107 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 5.3 Recommended Operating Conditions MIN NOM MAX UNIT Device supply voltage, I/O, VDDIO (1) 2.97 3.3 3.63 V Device supply voltage, Analog Subsystem, VDD18 1.71 1.8 1.995 (when internal VREG is disabled and 1.8 V is V supplied externally) Device supply voltage, Master and Control 1.14 1.2 1.32 Subsystems, VDD12 V (when internal VREG is disabled and 1.2 V is supplied externally) Supply ground, VSS 0 V Analog supply voltage, VDDA (1) 2.97 3.3 3.63 V Analog ground, VSSA 0 V Device clock frequency (system clock) H52C, H22C 2 100 Master Subsystem M52C, M22C, M20B 2 75 MHz E20B 2 60 Device clock frequency (system clock) H52C, H22C 2 150 Control Subsystem M52C, M22C, M20B 2 75 MHz E20B 2 60 High-level input voltage, VIH (3.3 V) VDDIO * 0.7 VDDIO + 0.3 V Low-level input voltage, VIL (3.3 V) VSS – 0.3 VDDIO * 0.3 V High-level output source current, VOH = VOH(MIN) , IOH All GPIO/AIO pins –4 mA Group 2(2) –8 mA Low-level output sink current, VOL = VOL(MAX), IOL All GPIO/AIO pins 4 mA Group 2(2) 8 mA Free-Air temperature, TA T version –40 105 S version –40 125 °C Q version (Q100 qualification) –40 125 Junction temperature, TJ T version –40 125 S version –40 150 °C Q version (Q100 qualification) –40 150 (1) VDDIO and VDDA should be maintained within approximately 0.3 V of each other. (2) Group 2 pins are as follows: PD3_GPIO19, PE2_GPIO26, PE3_GPIO27, PH6_GPIO54, PH7_GPIO55, EMU0, TDO, EMU1, PD0_GPIO16, AIO7, AIO4. 108 Device Operating Conditions Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 5.4 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH = IOH MAX VDDIO * 0.8 VOH High-level output voltage V IOH = 50 μA VDDIO – 0.2 VOL Low-level output voltage IOL = IOL MAX VDDIO * 0.2 V All GPIO pins –50 –230 Pin with pullup VDDIO = 3.3 V, VIN = 0 V XRS pin –50 –230 enabled Input current IIL μA ARS pin –100 –400 (low level) Pin with pulldown VDDIO = 3.3 V, VIN = 0 V ±2(1) enabled Pin with pullup VDDIO = 3.3 V, VIN = VDDIO ±2(1) enabled Input current IIH μA (high level) Pin with pulldown VDDIO = 3.3 V, VIN = VDDIO 50 200 enabled Output current, pullup or IOZ VO = VDDIO or 0 V ±2(1) μA pulldown disabled CI Input capacitance 2 pF Digital Subsystem POR reset Time after POR event is removed to XRS release 50 ?s release delay time Analog Subsystem POR reset Time after POR event is removed to ARS release 400 800 ?s release delay time VREG VDD18 output Internal VREG18 on 1.77 1.935 V VREG VDD12 output Internal VREG12 on 1.2 V (1) For GPIO38 and GPIO46 (USB OTG pins), this parameter is ±8 ?A. Copyright ? 2011–2014, Texas Instruments Incorporated Device Operating Conditions 109 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 6 Electrical Specifications 6.1 Current Consumption Table 6-1. Current Consumption at 150-MHz Cf20;BACKGROUND-COLOR:#4ae2f7">28x SYSCLKOUT and 75-MHz M3SSCLK VREG ENABLED VREG DISABLED MODE TEST CONDITIONS(1) IDDIO (2) IDDA IDD18 IDD12 IDDIO (2) IDDA TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX The following Cortex-M3 peripherals are exercised: ? I2C1 ? SSI1, SSI2 ? UART0, UART1, UART2 ? CAN0 ? USB ? ?DMA ? Timer0, Timer1 ? ?CRC ? WDOG0, WDOG1 ? Flash ? Internal Oscillator 1, Internal Oscillator 2 The following Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals are exercised: ? McBSP Operational ? eQEP1, eQEP2 – 325 mA – 40 mA – 25 mA – 225 mA – 65 mA – 40 mA (RAM) ? eCAP1, eCAP2, eCAP3, eCAP4 ? SCI-A ? SPI-A ? I2 C ? DMA ? VCU ? FPU ? Flash The following Analog peripherals are exercised: ? ADC1, ADC2 ? Comparator 1, Comparator 2, Comparator 3, Comparator 4, Comparator 5, Comparator 6 (1) The following is done in a loop: ? Code is running out of RAM. ? All I/O pins are left unconnected. ? All the communication peripherals are exercised in loop-back mode. ? USB – Only logic is exercised by loading and unloading FIFO. ? ?DMA does memory-to-memory transfer. ? DMA does memory-to-memory transfer. ? VCU – CRC calculated and checked. ? FPU – Float operations performed. ? ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled. ? Timers and Watchdog serviced. ? eCAP in APWM mode generates 36.6-kHz output on 4 pins. ? ADC performs continuous conversion. ? FLASH is continuously read and in active state. ? XCLKOUT is turned off. (2) IDDIO current is dependent on the electrical loading on the I/O pins. 110 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 6-1. Current Consumption at 150-MHz Cf20;BACKGROUND-COLOR:#4ae2f7">28x SYSCLKOUT and 75-MHz M3SSCLK (continued) VREG ENABLED VREG DISABLED MODE TEST CONDITIONS(1) IDDIO (2) IDDA IDD18 IDD12 IDDIO (2) IDDA TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX ? PLL is on. ? Cortex-M3 CPU is not executing. ? M3SSCLK is on. SLEEP IDLE – 145 mA – 2 mA – 20 mA – 110 mA – 10 mA – 2 mA ? Cf20;BACKGROUND-COLOR:#4ae2f7">28CLKIN is on. ? Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU is not executing. ? Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK is off. ? Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK is on. ? PLL is on. ? Cortex-M3 CPU is not executing. ? M3SSCLK is on. SLEEP – 125 mA – 2 mA – 20 mA – 90 mA – 10 mA – 2 mA STANDBY ? Cf20;BACKGROUND-COLOR:#4ae2f7">28CLKIN is off. ? Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU is not executing. ? Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK is off. ? Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK is off. ? PLL is off. ? Cortex-M3 CPU is not executing. ? M3SSCLK is 32 kHz. DEEP SLEEP – 75 mA – 2 mA – 5 mA – 60 mA – 6 mA – 2 mA STANDBY ? Cf20;BACKGROUND-COLOR:#4ae2f7">28CLKIN is off. ? Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU is not executing. ? Cf20;BACKGROUND-COLOR:#4ae2f7">28CPUCLK is off. ? Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK is off. Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 111 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 6-2. Current Consumption at 100-MHz Cf20;BACKGROUND-COLOR:#4ae2f7">28x SYSCLKOUT and 100-MHz M3SSCLK VREG ENABLED VREG DISABLED MODE TEST CONDITIONS(1) IDDIO (2) IDDA IDD18 IDD12 IDDIO (2) IDDA TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX The following Cortex-M3 peripherals are exercised: ? I2C1 ? SSI1, SSI2 ? UART0, UART1, UART2 ? CAN0 ? USB ? ?DMA ? Timer0, Timer1 ? ?CRC ? WDOG0, WDOG1 ? Flash ? Internal Oscillator 1, Internal Oscillator 2 The following Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals are exercised: ? McBSP Operational ? eQEP1, eQEP2 – 295 mA – 40 mA – 20 mA – 200 mA – 65 mA – 40 mA (RAM) ? eCAP1, eCAP2, eCAP3, eCAP4 ? SCI-A ? SPI-A ? I2 C ? DMA ? VCU ? FPU ? Flash The following Analog peripherals are exercised: ? ADC1, ADC2 ? Comparator 1, Comparator 2, Comparator 3, Comparator 4, Comparator 5, Comparator 6 (1) The following is done in a loop: ? Code is running out of RAM. ? All I/O pins are left unconnected. ? All the communication peripherals are exercised in loop-back mode. ? USB – Only logic is exercised by loading and unloading FIFO. ? ?DMA does memory-to-memory transfer. ? DMA does memory-to-memory transfer. ? VCU – CRC calculated and checked. ? FPU – Float operations performed. ? ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled. ? Timers and Watchdog serviced. ? eCAP in APWM mode generates 36.6-kHz output on 4 pins. ? ADC performs continuous conversion. ? FLASH is continuously read and in active state. ? XCLKOUT is turned off. (2) IDDIO current is dependent on the electrical loading on the I/O pins. 112 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 6-3. Current Consumption at 75-MHz Cf20;BACKGROUND-COLOR:#4ae2f7">28x SYSCLKOUT and 75-MHz M3SSCLK VREG ENABLED VREG DISABLED MODE TEST CONDITIONS(1) IDDIO (2) IDDA IDD18 IDD12 IDDIO (2) IDDA TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX The following Cortex-M3 peripherals are exercised: ? I2C1 ? SSI1, SSI2 ? UART0, UART1, UART2 ? CAN0 ? USB ? ?DMA ? Timer0, Timer1 ? ?CRC ? WDOG0, WDOG1 ? Flash ? Internal Oscillator 1, Internal Oscillator 2 The following Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals are exercised: ? McBSP Operational ? eQEP1, eQEP2 – 275 mA – 40 mA – 25 mA – 175 mA – 65 mA – 40 mA (RAM) ? eCAP1, eCAP2, eCAP3, eCAP4 ? SCI-A ? SPI-A ? I2 C ? DMA ? VCU ? FPU ? Flash The following Analog peripherals are exercised: ? ADC1, ADC2 ? Comparator 1, Comparator 2, Comparator 3, Comparator 4, Comparator 5, Comparator 6 (1) The following is done in a loop: ? Code is running out of RAM. ? All I/O pins are left unconnected. ? All the communication peripherals are exercised in loop-back mode. ? USB – Only logic is exercised by loading and unloading FIFO. ? ?DMA does memory-to-memory transfer. ? DMA does memory-to-memory transfer. ? VCU – CRC calculated and checked. ? FPU – Float operations performed. ? ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled. ? Timers and Watchdog serviced. ? eCAP in APWM mode generates 36.6-kHz output on 4 pins. ? ADC performs continuous conversion. ? FLASH is continuously read and in active state. ? XCLKOUT is turned off. (2) IDDIO current is dependent on the electrical loading on the I/O pins. Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 113 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 6-4. Current Consumption at 60-MHz Cf20;BACKGROUND-COLOR:#4ae2f7">28x SYSCLKOUT and 60-MHz M3SSCLK VREG ENABLED VREG DISABLED MODE TEST CONDITIONS(1) IDDIO (2) IDDA IDD18 IDD12 IDDIO (2) IDDA TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX The following Cortex-M3 peripherals are exercised: ? I2C1 ? SSI1, SSI2 ? UART0, UART1, UART2 ? CAN0 ? USB ? ?DMA ? Timer0, Timer1 ? ?CRC ? WDOG0, WDOG1 ? Flash ? Internal Oscillator 1, Internal Oscillator 2 The following Cf20;BACKGROUND-COLOR:#4ae2f7">28x peripherals are exercised: ? McBSP Operational ? eQEP1, eQEP2 – 250 mA – 40 mA – 20 mA – 155 mA – 65 mA – 40 mA (RAM) ? eCAP1, eCAP2, eCAP3, eCAP4 ? SCI-A ? SPI-A ? I2 C ? DMA ? VCU ? FPU ? Flash The following Analog peripherals are exercised: ? ADC1, ADC2 ? Comparator 1, Comparator 2, Comparator 3, Comparator 4, Comparator 5, Comparator 6 (1) The following is done in a loop: ? Code is running out of RAM. ? All I/O pins are left unconnected. ? All the communication peripherals are exercised in loop-back mode. ? USB – Only logic is exercised by loading and unloading FIFO. ? ?DMA does memory-to-memory transfer. ? DMA does memory-to-memory transfer. ? VCU – CRC calculated and checked. ? FPU – Float operations performed. ? ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled. ? Timers and Watchdog serviced. ? eCAP in APWM mode generates 36.6-kHz output on 4 pins. ? ADC performs continuous conversion. ? FLASH is continuously read and in active state. ? XCLKOUT is turned off. (2) IDDIO current is dependent on the electrical loading on the I/O pins. NOTE The peripheral-I/O multiplexing implemented in the device prevents all available peripherals from being used at the same time because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If the clocks to all the peripherals are turned on at the same time, the current drawn by the device will be more than the numbers specified in the current consumption table. 114 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 6.2 Thermal Design Considerations Based on the end-application design and operational profile, the IDD12, IDD18, and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. For more details about thermal metrics and definitions, see the Semiconductor and IC Package Thermal Metrics Application Report (literature number SPRA953) and the Reliability Data for TMS320LF24xx and TMS320Ff20;BACKGROUND-COLOR:#4ae2f7">28xx Devices Application Report (literature number SPRA963). Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 115 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 6.3 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their Letters and symbols and their meanings: meanings: a access time H High c cycle time (period) L Low d delay time V Valid Unknown, changing, or don't care f fall time X level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) 6.3.1 General Notes on Timing Parameters All output signals from the f20;BACKGROUND-COLOR:#4ae2f7">28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document. 6.3.2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document. A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Figure 6-1. 3.3-V Test Load Circuit 116 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 6.4 Clock Frequencies, Requirements, and Characteristics This section provides the frequencies and timing requirements of the input clocks; PLL lock times; frequencies of the internal clocks; and the frequency and switching characteristics of the output clock. 6.4.1 Input Clock Frequency and Timing Requirements, PLL Lock Times Table 6-5 shows the frequency requirements for the input clocks to the Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x devices. Table 6-6 shows the crystal equivalent series resistance requirements. Table 6-7, Table 6-8, Table 6-9, and Table 6- 10 show the timing requirements for the input clocks to the Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x devices. Table 6-11 shows the PLL lock times for the Main PLL and the USB PLL. The Main PLL operates from the X1 or X1/X2 input clock pins, and the USB PLL operates from the XCLKIN input clock pin. Table 6-5. Input Clock Frequency MIN MAX UNIT f(OSC) Frequency, X1/X2, from external crystal or resonator 2 20 MHz f(OCI) Frequency, X1, from external oscillator (PLL enabled) 2 30 MHz f(OCI) Frequency, X1, from external oscillator (PLL disabled) 2 100 MHz f(XCI) Frequency, XCLKIN, from external oscillator 2 60 MHz Table 6-6. Crystal Equivalent Series Resistance (ESR) Requirements(1) MAXIMUM ESR (Ω) MAXIMUM ESR (Ω) CRYSTAL FREQUENCY (MHz) (CL1/2 = 12 pF) (CL1/2 = 24 pF) 2 175 375 4 100 195 6 75 145 8 65 120 10 55 110 12 50 95 14 50 90 16 45 75 18 45 65 20 45 50 (1) Crystal shunt capacitance (C0) should be less than or equal to 7 pF. Table 6-7. X1 Timing Requirements - PLL Enabled(1) MIN MAX UNIT tf(OCI) Fall time, X1 6 ns tr(OCI) Rise time, X1 6 ns tw(OCL) Pulse duration, X1 low as a percentage of tc(OCI) 45 55 % tw(OCH) Pulse duration, X1 high as a percentage of tc(OCI) 45 55 % (1) The possible Main PLL configuration modes are shown in Table 3-20 to Table 3-23. Table 6-8. X1 Timing Requirements - PLL Disabled MIN MAX UNIT tf(OCI) Fall time, X1 Up to 20 MHz 6 ns 20 MHz to 100 MHz 2 tr(OCI) Rise time, X1 Up to 20 MHz 6 ns 20 MHz to 100 MHz 2 tw(OCL) Pulse duration, X1 low as a percentage of tc(OCI) 45 55 % tw(OCH) Pulse duration, X1 high as a percentage of tc(OCI) 45 55 % Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 117 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 6-9. XCLKIN Timing Requirements - PLL Enabled(1) MIN MAX UNIT tf(XCI) Fall time, XCLKIN 6 ns tr(XCI) Rise time, XCLKIN 6 ns tw(XCL) Pulse duration, XCLKIN low as a percentage of tc(XCI) 45 55 % tw(XCH) Pulse duration, XCLKIN high as a percentage of tc(XCI) 45 55 % (1) The possible USB PLL configuration modes are shown in Table 3-24 and Table 3-25. Table 6-10. XCLKIN Timing Requirements - PLL Disabled MIN MAX UNIT tf(XCI) Fall time, XCLKIN Up to 20 MHz 6 ns 20 MHz to 100 MHz 2 tr(XCI) Rise time, XCLKIN Up to 20 MHz 6 ns 20 MHz to 100 MHz 2 tw(XCL) Pulse duration, XCLKIN low as a percentage of tc(XCI) 45 55 % tw(XCH) Pulse duration, XCLKIN high as a percentage of tc(XCI) 45 55 % Table 6-11. PLL Lock Times MIN NOM MAX UNIT input clock t(PLL) Lock time, Main PLL (X1, from external oscillator) 2000(1) cycles input clock t(USB) Lock time, USB PLL (XCLKIN, from external oscillator) 2000(1) cycles (1) For example, if the input clock to the PLL is 10 MHz, then the PLL lock time is 100 ns x 2000 = 200 ?s. 6.4.2 Internal Clock Frequencies Table 6-12 provides the clock frequencies for the internal clocks of the Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x devices. Table 6-12. Internal Clock Frequencies (150-MHz Devices) MIN NOM MAX UNIT f(USB) Frequency, USBPLLCLK 60 MHz f(PLL) Frequency, PLLSYSCLK 2 150 MHz f(OCK) Frequency, OSCCLK 2 100 MHz f(M3C) Frequency, M3SSCLK 2 100(1) MHz f(ADC) Frequency, ASYSCLK 2 37.5 MHz f(SYS) Frequency, Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK 2 150(1) MHz f(HSP) Frequency, Cf20;BACKGROUND-COLOR:#4ae2f7">28HSPCLK 2 150(1) MHz f(LSP) Frequency, Cf20;BACKGROUND-COLOR:#4ae2f7">28LSPCLK(2) 2 37.5(3) 150(1) MHz f(10M) Frequency, 10MHzCLK 10 MHz f(32K) Frequency, 32KHzCLK 32 kHz (1) An integer divide ratio must be maintained between the Cf20;BACKGROUND-COLOR:#4ae2f7">28x and Cortex-M3 clock frequencies. For example, when the Cf20;BACKGROUND-COLOR:#4ae2f7">28x is configured to run at a maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex-M3 will be 75 MHz. See Figure 3- 10 and Figure 3-12 to see the internal clocks and clock divider options. (2) Lower LSPCLK will reduce device power consumption. (3) This is the default reset value if Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK = 150 MHz. 118 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 6.4.3 Output Clock Frequency and Switching Characteristics Table 6-13 provides the frequency of the output clock from the Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x devices. Table 6-14 shows the switching characteristics of the output clock from the Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x devices, XCLKOUT. Table 6-13. Output Clock Frequency MIN MAX UNIT f(XCO) Frequency, XCLKOUT 2 37.5 MHz Table 6-14. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2) over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tf(XCO) Fall time, XCLKOUT 5 ns tr(XCO) Rise time, XCLKOUT 5 ns tw(XCOL) Pulse duration, XCLKOUT low H – 2 H + 2 ns tw(XCOH) Pulse duration, XCLKOUT high H – 2 H + 2 ns (1) A load of 40 pF is assumed for these parameters. (2) H = 0.5tc(XCO) Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 119 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 6.5 Power Sequencing There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up and power down. (All I/Os, except for GPIO135, are glitch-free during power up and power down.) No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, this value is 0.7 V above VDDA) prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results. A. Upon power up, PLLSYSCLK is OSCCLK/8. Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, PLLSYSCLK is further divided by 4 before PLLSYSCLK appears at XCLKOUT. XCLKOUT = OSCCLK/32 during this phase. B. Boot ROM configures the SYSDIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that XCLKOUT will not be visible at the pin until explicitly configured by user code. C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will be based on user environment and could be with or without PLL enabled. D. Using the XRS pin is optional due to the on-chip POR circuitry. Figure 6-2. Power-On Reset 120 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 6-15. Reset (XRS) Timing Requirements MIN MAX UNIT th(boot-mode) (1) Hold time for boot-mode pins 14000tc(M3C) cycles tw(RSL2) Pulse duration, XRS low on warm reset 32tc(OCK) cycles (1) The minimum hold time for boot mode pins is 23 times longer for silicon revision 0 devices. Table 6-16. Reset (XRS) Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tw(RSL1) Pulse duration, XRS driven by device 600 μs tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OCK) cycles td(EX) Delay time, address/data valid after XRS high 32tc(OCK) cycles tINTOSCST Start up time, internal zero-pin oscillator 3 μs tOSCST (1) On-chip crystal-oscillator start-up time 1 10 ms (1) Dependent on crystal/resonator and board design. A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will be based on user environment and could be with or without PLL enabled. Figure 6-3. Warm Reset Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 121 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 6.5.1 Changing the Frequency of the Main PLL Figure 6-4 shows how to change the frequency of the Main PLL. The three steps are described below: 1. The PLL must first be placed in bypass mode (by writing to the SYSPLLCTL register) before any changes are made to the SPLLIMULT and SPLLFMULT fields of the SYSPLLMULT Register. Figure 6- 4 shows that before being placed in bypass mode, the internal PLLSYSCLK clock was operating at 100 MHz. After entering the bypass mode, the PLLSYSCLK becomes 10 MHz, which is the frequency of OSCCLK, the input clock to the PLL 2. Once the PLL is placed in bypass mode, the SYSPLLMULT register can be modified to increase the PLLSYSCLK frequency to 150 MHz. See Figure 6-4 for the settings of the SPLLIMULT (integer) and SPLLFMULT (fractional) multiply fields of the SYSPLLMULT register for this step, and see Figure 3-8 for the functional description of the Main PLL. The PLL bypass mode must be maintained for at least 2000 OSCCLK cycles in order for the PLL to properly lock to the new frequency. 3. Finally, the SYSPLLCTL register is written to again, this time to take the PLL out of the bypass mode. Following this step, the PLLSYSCLK switches over from 10 MHz to the new frequency of 150 MHz. Figure 6-4. Changing the Frequency of the Main PLL 122 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 6.5.2 Power Management and Supervisory Circuit Solutions Table 6-17 lists the power management and supervisory circuit solutions for Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x devices. LDO selection depends on the total power consumed in the end application. Go to www.ti.com and click on Power Management for a complete list of TI power ICs or select the Power Management Selection Guide link for specific power reference designs. Table 6-17. Power Management and Supervisory Circuit Solutions SUPPLIER TYPE PART DESCRIPTION Texas Instruments DC/DC TPS62160/170 1/0.5-A, 3–17-V input, step-down converter in 2x2 QFN package Texas Instruments DC/DC TPS62140/150 2/1-A, 3–17-V input, step-down converter in 3x3 QFN package Texas Instruments LDO TPS7A8001 Low-noise, high-bandwidth PSRR, 1A low-dropout linear regulator Texas Instruments LDO TPS7A7001 2A, single-output, very-low input, adjustable low-dropout linear regulator Texas Instruments DC/DC LM22672/1 1/0.5-A, 4.5–42-V input SIMPLE SWITCHER?, step-down voltage regulator with features Texas Instruments DC/DC TPS54160/060 3.5-V to 60-V input, 1.5/0.5-A step-down converter with Eco-Mode Texas Instruments Module LMZ10501 1A SIMPLE SWITCHER? Nano Module with 5.5-V maximum input voltage Texas Instruments SVS TPS386000/040 Quad supply voltage supervisors with programmable delay and watchdog timer Texas Instruments LDO TPS73719 Single-output LDO, 1-A, fixed (1.9-V), reverse-current protection Texas Instruments LDO TPS73534 Single-output LDO, 500-mA, fixed (3.4-V), low-quiescent current, low-noise, high PSRR Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 123 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 6.6 Flash Timing – Master Subsystem Table 6-18. Master Subsystem – Flash/OTP Endurance for T Temperature Material(1) ERASE/PROGRAM MIN TYP MAX UNIT TEMPERATURE Nf Flash endurance for the array (write/erase cycles) 0°C to 105°C (ambient) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) 0°C to 105°C (ambient) 1 write (1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 6-19. Master Subsystem – Flash/OTP Endurance for S Temperature Material(1) ERASE/PROGRAM MIN TYP MAX UNIT TEMPERATURE Nf Flash endurance for the array (write/erase cycles) 0°C to 125°C (ambient) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) 0°C to 125°C (ambient) 1 write (1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 6-20. Master Subsystem – Flash/OTP Endurance for Q Temperature Material(1) ERASE/PROGRAM MIN TYP MAX UNIT TEMPERATURE Nf Flash endurance for the array (write/erase cycles) –40°C to 125°C (ambient) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) –40°C to 125°C (ambient) 1 write (1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 6-21. Master Subsystem – Flash Parameters at 60 MHz(1) TEST PARAMETER MIN TYP MAX UNIT CONDITIONS IDDP (2)(3) VDD current consumption during Erase/Program cycle VREG disabled 80 mA IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle 50 IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle VREG enabled 145 mA (1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations. (2) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed during the programming process. (3) This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral. 124 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 6-22. Master Subsystem – Flash Parameters at 75 MHz(1) TEST PARAMETER MIN TYP MAX UNIT CONDITIONS IDDP (2)(3) VDD current consumption during Erase/Program cycle VREG disabled 105 mA IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle 55 IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle VREG enabled 195 mA (1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations. (2) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed during the programming process. (3) This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral. Table 6-23. Master Subsystem – Flash Parameters at 100 MHz(1) TEST PARAMETER MIN TYP MAX UNIT CONDITIONS IDDP (2)(3) VDD current consumption during Erase/Program cycle VREG disabled 105 mA IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle 55 IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle VREG enabled 195 mA (1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations. (2) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed during the programming process. (3) This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral. Table 6-24. Master Subsystem – Flash/OTP Access Timing(1) PARAMETER MIN MAX UNIT ta(f) Flash access time 25 ns ta(OTP) OTP access time 50 ns (1) Access time numbers shown in this table are prior to device characterization. Final numbers will be published in the datasheet for the fully qualified production device. Table 6-25. Master Subsystem – Flash Data Retention Duration PARAMETER TEST CONDITIONS MIN MAX UNIT tretention Data retention duration TJ = 85°C 20 years Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 125 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 6-26. Master Subsystem – Minimum Required Flash/OTP Wait-States at Different Frequencies SYSCLKOUT (MHz) SYSCLKOUT (ns) WAIT-STATE 100 10 2 90 11.11 2 80 12.5 1 70 14.29 1 60 16.67 1 50 20 1 40 25 0 30 33.33 0 20 50 0 10 100 0 The equation to compute the Flash wait-state in Table 6-26 is as follows: round up to the next integer, or 1, whichever is larger. 126 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 6.7 Flash Timing – Control Subsystem Table 6-27. Control Subsystem – Flash/OTP Endurance for T Temperature Material(1) ERASE/PROGRAM MIN TYP MAX UNIT TEMPERATURE Nf Flash endurance for the array (write/erase cycles) 0°C to 105°C (ambient) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) 0°C to 105°C (ambient) 1 write (1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 6-f20;BACKGROUND-COLOR:#4ae2f7">28. Control Subsystem – Flash/OTP Endurance for S Temperature Material(1) ERASE/PROGRAM MIN TYP MAX UNIT TEMPERATURE Nf Flash endurance for the array (write/erase cycles) 0°C to 125°C (ambient) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) 0°C to 125°C (ambient) 1 write (1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 6-29. Control Subsystem – Flash/OTP Endurance for Q Temperature Material(1) ERASE/PROGRAM MIN TYP MAX UNIT TEMPERATURE Nf Flash endurance for the array (write/erase cycles) –40°C to 125°C (ambient) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) –40°C to 125°C (ambient) 1 write (1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 6-30. Control Subsystem – Flash Parameters at 60 MHz(1) TEST PARAMETER MIN TYP MAX UNIT CONDITIONS IDDP (2)(3) VDD current consumption during Erase/Program cycle VREG disabled 90 mA IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle 55 IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle VREG enabled 150 mA (1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations. (2) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed during the programming process. (3) This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral. Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 127 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 6-31. Control Subsystem – Flash Parameters at 100 MHz(1) TEST PARAMETER MIN TYP MAX UNIT CONDITIONS IDDP (2)(3) VDD current consumption during Erase/Program cycle VREG disabled 90 mA IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle 55 IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle VREG enabled 150 mA (1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations. (2) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed during the programming process. (3) This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral. Table 6-32. Control Subsystem – Flash Parameters at 150 MHz(1) TEST PARAMETER MIN TYP MAX UNIT CONDITIONS IDDP (2)(3) VDD current consumption during Erase/Program cycle VREG disabled 90 mA IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle 55 IDDIOP (2)(3) VDDIO current consumption during Erase/Program cycle VREG enabled 150 mA (1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations. (2) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed during the programming process. (3) This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral. Table 6-33. Control Subsystem – Flash/OTP Access Timing(1) PARAMETER MIN MAX UNIT ta(f) Flash access time 25 ns ta(OTP) OTP access time 50 ns (1) Access time numbers shown in this table are prior to device characterization. Final numbers will be published in the datasheet for the fully qualified production device. Table 6-34. Control Subsystem – Flash Data Retention Duration PARAMETER TEST CONDITIONS MIN MAX UNIT tretention Data retention duration TJ = 85°C 20 years 1f20;BACKGROUND-COLOR:#4ae2f7">28 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 6-35. Control Subsystem – Minimum Required Flash/OTP Wait-States at Different Frequencies SYSCLKOUT (MHz) SYSCLKOUT (ns) WAIT-STATE 150 6.7 3 140 7.14 3 130 7.7 3 120 8.33 2 110 9.1 2 100 10 2 90 11.11 2 80 12.5 1 70 14.29 1 60 16.67 1 50 20 1 40 25 0 30 33.33 0 20 50 0 10 100 0 The equation to compute the Flash wait-state in Table 6-35 is as follows: round up to the next integer, or 1, whichever is larger. Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 129 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 6.8 GPIO Electrical Data and Timing 6.8.1 GPIO - Output Timing Table 6-36. General-Purpose Output Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tr(GPO) Rise time, GPIO switching low to high All GPIOs 8 ns tf(GPO) Fall time, GPIO switching high to low All GPIOs 8 ns tfGPO Toggling frequency, GPO pins 25 MHz Figure 6-5. General-Purpose Output Timing 130 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 6.8.2 GPIO - Input Timing Table 6-37. General-Purpose Input Timing Requirements MIN MAX UNIT QUALPRD = 0 1tc(SCO) cycles tw(SP) Sampling period QUALPRD ≠ 0 2tc(SCO) * QUALPRD cycles tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles Synchronous mode 2tc(SCO) cycles tw(GPI) (2) Pulse duration, GPIO low/high With input qualifier tw(IQSW) + tw(SP) + 1tc(SCO) cycles (1) "n" represents the number of qualification samples as defined by GPxQSELn register. (2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal. A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled). B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins. C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used. D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition. Figure 6-6. Sampling Mode Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 131 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 6.8.3 Sampling Window Width for Input Signals The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT. Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0 Sampling frequency = SYSCLKOUT, if QUALPRD = 0 Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0 In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT. Sampling period = SYSCLKOUT cycle, if QUALPRD = 0 In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. This is determined by the value written to GPxQSELn register. Case 1: Qualification using 3 samples Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0 Case 2: Qualification using 6 samples Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0 Figure 6-7. General-Purpose Input Timing 132 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 6.8.4 Low-Power Mode Wakeup Timing Table 6-38 shows the timing requirements, Table 6-39 shows the switching characteristics, and Figure 6-8 shows the timing diagram for IDLE mode. Table 6-38. IDLE Mode Timing Requirements(1) MIN MAX UNIT Without input qualifier 2tc(SCO) Pulse duration, external wake-up tw(WAKE-INT) cycles signal With input qualifier 5tc(SCO) + tw(IQSW) (1) For an explanation of the input qualifier parameters, see Table 6-37. Table 6-39. IDLE Mode Switching Characteristics(1) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT Delay time, external wake signal to program execution resume (2) Wake-up from Flash Without input qualifier 20tc(SCO) cycles ? Flash module in active state With input qualifier 20tc(SCO) + tw(IQSW) td(WAKE-IDLE) Wake-up from Flash Without input qualifier 1050tc(SCO) cycles ? Flash module in sleep state With input qualifier 1050tc(SCO) + tw(IQSW) Without input qualifier 20tc(SCO) cycles ? Wake-up from SARAM With input qualifier 20tc(SCO) + tw(IQSW) (1) For an explanation of the input qualifier parameters, see Table 6-37. (2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up) signal involves additional latency. A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS. B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-8. IDLE Entry and Exit Timing Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 133 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 6-40. STANDBY Mode Timing Requirements MIN MAX UNIT Without input qualification 3tc(OSCCLK) Pulse duration, external tw(WAKE-INT) cycles wake-up signal With input qualification(1) (2 + QUALSTDBY) * tc(OSCCLK) (1) QUALSTDBY is a 6-bit field in the LPMCR0 register. Table 6-41. STANDBY Mode Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT Delay time, IDLE instruction executed td(IDLE-XCOL) 32tc(SCO) 45tc(SCO) cycles to XCLKOUT low Delay time, external wake signal to td(WAKE-STBY) cycles program execution resume(1) Without input qualifier 100tc(SCO) ? Wake up from flash cycles – Flash module in active state With input qualifier 100tc(SCO) + tw(WAKE-INT) Without input qualifier 1125tc(SCO) ? Wake up from flash cycles – Flash module in sleep state With input qualifier 1125tc(SCO) + tw(WAKE-INT) Without input qualifier 100tc(SCO) cycles ? Wake up from SARAM With input qualifier 100tc(SCO) + tw(WAKE-INT) (1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up signal) involves additional latency. 134 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 A. IDLE instruction is executed to put the device into STANDBY mode. B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off: ? 16 cycles, when DIVSEL = 00 or 01 ? 32 cycles, when DIVSEL = 10 ? 64 cycles, when DIVSEL = 11 This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its access time is longer than this number then it will fail. It is recommended to enter STANDBY mode from SARAM without an XINTF access in progress. C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. D. The external wake-up signal is driven active. E. After a latency period, the STANDBY mode is exited. F. Normal execution resumes. The device will respond to the interrupt (if enabled). G. From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-9. STANDBY Entry and Exit Timing Diagram Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 135 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 6-42. HALT Mode Timing Requirements MIN MAX UNIT tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) (1) cycles tw(WAKE-XRS) Pulse duration, XRS wakeup signal toscst + 8tc(OSCCLK) cycles (1) See Table 6-16 for an explanation of toscst. Table 6-43. HALT Mode Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles tp PLL lock-up time 131072tc(OSCCLK) cycles Delay time, PLL lock to program execution resume 1125tc(SCO) cycles ? Wake up from flash td(WAKE-HALT) – Flash module in sleep state 35tc(SCO) cycles ? Wake up from SARAM 136 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 A. IDLE instruction is executed to put the device into HALT mode. B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off and the CLKIN to the core is stopped: ? 16 cycles, when DIVSEL = 00 or 01 ? 32 cycles, when DIVSEL = 10 ? 64 cycles, when DIVSEL = 11 This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its access time is longer than this number then it will fail. It is recommended to enter HALT mode from SARAM without an XINTF access in progress. C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be taken to maintain a low noise environment prior to entering and during HALT mode. E. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or XCLKIN) cycles. Note that these 131,072 clock cycles are applicable even when the PLL is disabled (that is, code execution will be delayed by this duration even when the PLL is disabled). F. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after a latency. G. Normal operation resumes. H. From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-10. HALT Wake-Up Using GPIOn Copyright ? 2011–2014, Texas Instruments Incorporated Electrical Specifications 137 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 6.9 External Interrupt Electrical Data and Timing Table 6-44. External Interrupt Timing Requirements(1) MIN MAX UNIT tw(INT) (2) Pulse duration, INT input low/high Synchronous 1tc(SCO) cycles With qualifier 1tc(SCO) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-37. (2) This timing is applicable to any GPIO pin configured for ADCSOC functionality. Table 6-45. External Interrupt Switching Characteristics(1) over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(INT) Delay time, INT low/high to interrupt-vector fetch tw(IQSW) + 12tc(SCO) cycles (1) For an explanation of the input qualifier parameters, see Table 6-37. Figure 6-11. External Interrupt Timing 138 Electrical Specifications Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7 Peripheral Information and Timings 7.1 Analog and Shared Peripherals Concerto Shared Peripherals are accessible from both the Master Subsystem and the Control Subsystem. The Analog Shared Peripherals include two 12-bit ADCs (Analog-to-Digital Converters), and six Comparator + DAC (10-bit) modules. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other analog registers, such as the ADC Configuration and Comparator Registers, are accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU only. The Digital Shared Peripherals include the IPC peripheral and the EPI. IPC is accessible by both CPUs; EPI is accessible by both CPUs and both DMAs. IPC is used for sending and receiving synchronization events between Master and Control subsystems to coordinate execution of software running on both processors, or exchanging of data between the two processors. EPI is used by this device to communicate with external memory and other devices. For detailed information on the processor peripherals, see the Concerto Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Technical Reference Manual (literature number SPRUH22). 7.1.1 Analog-to-Digital Converter Figure 7-1 shows the internal structure of each of the two ADC peripherals that are present on Concerto. Each ADC has 16 channels that can be programmed to select analog inputs, select start-of-conversion trigger, set the sampling window, and select end-of-conversion interrupt to prompt a CPU or DMA to read 16 result registers. The 16 ADC channels can be used independently or in pairs, based on the assignments inside the SAMPLEMODE register. Pairing up the channels allows two analog inputs to be sampled simultaneously—thereby, increasing the overall conversion performance. 7.1.1.1 Sample Mode Each ADC has 16 programmable channels that can be independently programmed for analog-to-digital conversion when corresponding bits in the SAMPLEMODE register are set to Sequential Mode. For example, if bit 2 in the SAMPLEMODE register is set to 0, ADC channels 4 and 5 are set to sequential mode. Both the SOC4CTL and SOC5CTL registers can then be programmed to configure channels 4 and 5 to independently perform analog-to-digital conversions with results being stored in the RESULT4 and RESULT5 registers. "Independently" means that channel 4 may use a different SOC trigger, different analog input, and different sampling window than the trigger, input, and window assigned to channel 5. The 16 programmable channels for each ADC may also be grouped in 8 channel pairs when corresponding bits in the SAMPLEMODE register are set to Simultaneous Mode. For example, if bit 2 in the SAMPLEMODE register is set to 1, ADC channels 4 and 5 are set to Simultaneous Mode. The SOC4CTL register now contains configuration parameters for both channel 4 and channel 5, and the SOC5CTL register is ignored. While channel 4 and channel 5 are still using dedicated analog inputs (now selected as pairs in the CHSEL field of SOC4CTL), they both share the same SOC trigger and Sampling Window, with the results being stored in the RESULT4 and RESULT5 registers. The Simultaneous mode is made possible by two sample-and-hold units present in each ADC. Each sample-and-hold unit has its own mux for selecting analog inputs (see Figure 7-1). By programming the SAMPLEMODE register, the 16 available channels can be configured as 16 independent channels, 8 channel pairs, or any combination thereof (for example, 10 sequential channels and 3 simultaneous pairs). Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 139 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 7-1. ADC 140 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.1.1.2 Start-of-Conversion Triggers There are eight external SOC triggers that go to each of the two ADC modules (from the Control Subsystem). In addition to the eight external SOC triggers, there are also two internal SOC triggers derived from EOC interrupts inside each ADC module (ADCINT1 and ADCINT2). Registers INTSOCSEL1 and 2 are used to configure each of the 16 ADC channels for internal or external SOC sources. If internal SOC is chosen for a given channel, the INTSOCSEL1 and 2 registers also select whether the internal source is ADCINT1 or ADCINT2. If external SOC is chosen for a given ADC channel, the TRIGSEL field of the corresponding SOCxCTL register selects which of the eight external triggers is used for SOC in that channel. One analog-to-digital conversion can be performed at a time by the 12-bit ADC. The analog-to- digital conversion priority is managed according to the state of the PRICTL register. 7.1.1.3 Analog Inputs Analog inputs to each of the two ADC modules are organized in two groups—A and B, with each group having a dedicated mux and sample-and-hold unit (see Figure 7-1). Mux A selects one of six possible analog inputs via AIO MUX. Mux B selects one of five possible analog inputs—four external inputs via AIO MUX, and one from the internal VREFLO signal, which is currently tied to the Analog Ground. The Mux A and Mux B inputs can be simultaneously or sequentially sampled by the two sample-and-hold units according to the sampling window chosen in the SOCxCTL register for the corresponding channel. 7.1.1.4 ADC Result Registers and EOC Interrupts Concerto analog-to-digital conversion results are stored in 32 Results Registers (16 for ADC1 and 16 for ADC2). The 16 ADCx channels can be programmed via the INTSELxNy registers to trigger up to eight ADCINT interrupts per ADC module, when their results are ready to be read. The eight ADCINT interrupts from ADC1 and the eight ADCINT interrupts from ADC2 are AND-ed together before propagating to both the Master Subsystem and the Control Subsystem, announcing that the Result Registers are ready to be read by a CPU or DMA (see Figure 3-3). Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 141 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.1.1.5 ADC Electrical Data and Timing Table 7-1. ADC Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT DC SPECIFICATIONS Resolution 12 Bits ADC clock 2 37.5 MHz Sample Window 7 64 ADC Clocks ACCURACY INL (Integral nonlinearity) –4 4 LSB DNL (Differential nonlinearity) –1 1.5 LSB Offset error Executing a single self- –20 0 20 LSB recalibration Executing periodic self- –4 0 4 recalibration Overall gain error with internal reference –60 60 LSB Overall gain error with external reference –40 40 LSB Channel-to-channel offset variation –4 4 LSB Channel-to-channel gain variation –4 4 LSB VREFLO input current –100 ?A VREFHI input current 100 ?A ANALOG INPUT Analog input voltage with internal reference 0 3.3 V Analog input voltage with external reference VREFLO VREFHI V VREFLO input voltage VSSA 0.66 V VREFHI input voltage 2.64 VDDA V Input capacitance 5 pF Input leakage current ±2 μA ADDITIONAL ADC SNR 65 dB ADC SINAD 62 dB ADC THD (50 kHz) –65 dB ENOB (SNR) 10.1 Bits SFDR 66 dB 142 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 A. Gain error contribution is based on sampling of full-scale voltage using internal reference mode. B. Periodic ADC offset re-cal is assumed. C. Total error shown represents the absolute value of possible error. Figure 7-2. Typical ADC Total Error [Temperature (°C) versus Total Error (LSBs)] Table 7-2. External ADC Start-of-Conversion Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(HCO) cycles Figure 7-3. ADCSOCAO or ADCSOCBO Timing 7.1.2 Comparator + DAC Units Figure 7-4 shows the internal structure of the six analog Comparator + DAC units present in Concerto devices. Each unit compares two analog inputs (A and B) and assigns a value of '1' when the voltage of the A input is greater than that of the B input, or a value of '0' when the opposite is true. The six A inputs and two B inputs come from AIO_MUX1 and AIO_MUX2. All six B inputs can also be provided by the 10- bit digital-to-analog units that are present in each comparator DAC. The 10-bit value for each DAC unit is programmed in the respective DACVAL register. Another comparator register, COMPCTL, can be programmed to select the source of the B input, to enable or disable the comparator circuit, to invert comparator output, to synchronize comparator output to Cf20;BACKGROUND-COLOR:#4ae2f7">28x SYSCLK, and to select the qualification period (number of clock cycles). All six output signals from the six comparators can be routed out to the device pins via GPIO_MUX2 pin mux. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 143 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 7-4. Comparator + DAC Units 144 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.1.2.1 On-Chip Comparator and DAC Electrical Data and Timing Table 7-3. Electrical Characteristics of the Comparator/DAC over recommended operating conditions (unless otherwise noted) CHARACTERISTIC MIN TYP MAX UNITS Comparator Comparator Input Range VSSA – VDDA V Comparator response time to PWM Trip Zone (Async) 30 ns Input Offset ±5 mV Input Hysteresis(1) 35 mV DAC DAC Output Range VSSA – VDDA V DAC resolution 10 bits DAC settling time See Figure 7-5 DAC Gain –1.5 % DAC Offset 10 mV Monotonic Yes INL ±3 LSB (1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback resistance between the output of the comparator and the non-inverting input of the comparator. Figure 7-5. DAC Settling Time Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 145 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.1.3 Interprocessor Communications Figure 7-6 shows the internal structure of the IPC peripheral used to synchronize program execution and exchange of data between the Cortex-M3 and the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU. IPC can be used by itself when synchronizing program execution or it can be used in conjunction with Message RAMs when coordinating data transfers between processors. In either case, the operation of the IPC is the same. There are two independent sides to the IPC peripheral—MTOC (Master to Control) and CTOM (Control to Master). The MTOC IPC is used by the Master Subsystem to send events to the Control Subsystem. The MTOC IPC typically sends events to the Control Subsystem by using the following registers: MTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS (2) , and MTOCIPCACK. Each of the 32 bits of these registers represents 32 independent channels through which the Cortex-M3 CPU can send up to 32 events to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU via software handshaking. Additionally, the first 4 bits of the MTOCIPC registers are supplemented with interrupts. To send an event via channel 2 from Cortex-M3 to Cf20;BACKGROUND-COLOR:#4ae2f7">28x, for example, the Cortex-M3 and Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPUs use bit 2 of the MTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS, MTOCIPCACK registers. The handshake starts with the Cortex-M3 polling bit 2 of the MTOCIPCFLG register to make sure bit 2 is '0'. Next, the Cortex-M3 writes a '1' into bit 2 of the MTOCIPCSET register to start the handshake. In the mean time, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x is continually polling the MTOCIPCSTS register while waiting for the message. As soon as the Cortex-M3 writes '1' to bit 2 of the MTOCIPCSET register, bit 2 of MTOCIPCFLG/MTOCIPCSTS also turns '1', thus announcing the event to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x. As soon as the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU reads a '1' from the MTOCIPCSTS register, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU should acknowledge by writing a '1' to bit 2 of the MTOCIPCACK register, which in turn, clears bit 2 of the MTOCIPCFLG/MTOCIPCSTS register, enabling the Cortex-M3 to send another message. Since the first four channels (bits 0, 1, 2, 3) are backed up by interrupts, both processors in the above example can use IPC interrupt 2 instead of polling to increase performance. A similar handshake is also used when sending data (not just event) from the Master Subsystem to the Control Subsystem, but with two additional steps. Before setting a bit in the MTOCIPCSET register, the Cortex-M3 should first load the MTOC Message RAM with a block of data that is to be made available to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x. In the second additional step, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x should read the data before setting a bit in the MTOCIPCACK register. This way, no data gets lost during multiple data transfers through a given block of the message RAM. The CTOM IPC is used by the Control Subsystem to send events to the Master Subsystem. The CTOM IPC typically sends events to the Master Subsystem by using the following three registers: CTOMIPCSET, CTOMIPCFLG/CTOMIPCSTS, and CTOMIPCACK. The process is exactly the same as that for the MTOC IPC communication above. (2) Note that physically MTOCIPCFLG/MTOCIPCSTS is one register, but it is referred to as the MTOCIPCFLG register when the Cortex-M3 CPU reads it, and as the MTOCIPCSTS register when the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU reads it. 146 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 7-6. IPC Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 147 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.1.4 External Peripheral Interface The EPI provides a high-speed parallel bus for interfacing external peripherals and memory. EPI is accessible from both the Master Subsystem and the Control Subsystem. EPI has several modes of operation to enable glueless connectivity to most types of external devices. Some EPI modes of operation conform to standard microprocessor address/data bus protocols, while others are tailored to support a variety of fast custom interfaces, such as those communicating with field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). The EPI peripheral can be accessed by the Cortex-M3 CPU, the Cortex-M3 DMA, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU, and the Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA over the high-performance AHB bus. The Cortex-M3 CPU and the ?DMA drive AHB bus cycles directly through the Cortex-M3 Bus Matrix. The Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU and DMA also connect to the Cortex-M3 Bus Matrix, but not directly. Before entering the Cortex-M3 Bus Matrix, the native Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU and DMA bus cycles are first converted to AHB protocol inside the MEM32-to-AHB Bus Bridge. After that, they pass through the Frequency Gasket to reduce the bus frequency by a factor of 2 or 4. Inside the Cortex-M3 Bus Matrix, the Cortex-M3 bus cycles may have to compete with Cf20;BACKGROUND-COLOR:#4ae2f7">28x bus cycles for access to the AHB bus on the way to the EPI peripheral. See Figure 7-7 to see how EPI interfaces to the Concerto Master Subsystem, the Concerto Control Subsystem, Resets, Clocks, and Interrupts. NOTE The Control Subsystem has no direct access to EPI in silicon revision 0 devices. Depending on how the Real-Time Window registers are configured inside the Bus Matrix, the arbitration between the Cortex-M3 and Cf20;BACKGROUND-COLOR:#4ae2f7">28x bus cycles is fixed-priority with Cortex-M3 having higher priority than Cf20;BACKGROUND-COLOR:#4ae2f7">28x, or the Cf20;BACKGROUND-COLOR:#4ae2f7">28x having the option to own the Bus Matrix for a fixed period of time (window)—effectively stalling all Cortex-M3 accesses during that time. Another EPI register inside the Cortex-M3 Bus Matrix is the Memory Protection Register, which enables assignments of chip-select spaces to Cortex-M3 or Cf20;BACKGROUND-COLOR:#4ae2f7">28x EPI accesses (or both). The assignments of chip-select spaces prevent a bus cycle (from any processor) that does not own a given chip-select space, from getting through to EPI. The Real-time Window registers are the only EPI-related registers that are configurable by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x. The Memory Protection Register is configurable only by the Cortex-M3 CPU, as are all configuration registers inside the EPI peripheral. Figure 7-7 shows the EPI registers and how they relate to individual blocks within the EPI. Once a bus cycle arrives at the AHB bus interface inside the EPI peripheral, the bus cycle is routed to the General-Purpose Block, SDRAM Block, or the Host Bus Module, depending on the operating mode chosen through the EPI Configuration Register. Write cycles are buffered in a 4-word-deep Write FIFO; therefore, in most cases, the write cycles do not stall the CPU or DMA unless the Write FIFO becomes full. Read cycles can be handled in two different ways: blocking read cycles and non-blocking read cycles. Blocking read cycles are implemented when the content of a Read Data Register is 0. Blocking reads stall the CPU or DMA until the bus transaction completes. Non-blocking read cycles are triggered when a non- zero value is written into a Read Data Register. A non-zero value being written into a Read Data register triggers EPI to autonomously perform multiple data reads in the background (without involving CPU or DMA) according to values stored inside the Read Address Register and the Read Size Register. The incoming data is then temporarily stored in the Non-Blocking Read (NBR) FIFO until an EPI interrupt is generated to prompt the CPU or DMA to read the FIFO without risk of stalling. Furthermore, EPI has actually two sets of Data/Address/Size registers (set 0 and set 1) to enable ping-pong operation of non- blocking reads. In a ping-pong operation, while the previously fetched data is being read by the CPU or DMA from one end of the NBR FIFO, the next set of data words is simultaneously being deposited into the other end of the NBR FIFO. 148 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 7-7. EPI Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 149 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn EPI can directly interrupt the Cortex-M3 CPU, the Cortex-M3 uDMA, and the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU (but not the Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA) via the EPI interrupt. Typically, EPI interrupts are used to prompt the CPU or DMA to move data to and from EPI. There are four EPI Interrupt registers that control various facets of interrupt generation, clearing, and masking. The EPI Interrupt can trigger ?DMA to perform reads and writes through DMA Channels 20 and 22. If a CPU is the intended recipient, the Cortex-M3 CPU is interrupted by NVIC vector 69, and the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU is interrupted through the INT12/INTx6 vector to the PIE. During EPI bus cycles, addresses entering the EPI module can propagate unchanged to the pins, or be remapped to different addresses according to values stored in the EPI Address Map Register in conjunction with the most significant bit of the incoming address. The EPI's three primary operating modes are: the General-Purpose Mode, the SDRAM Mode, and the Host Bus Mode (including 8-bit and 16-bit versions). 7.1.4.1 EPI General-Purpose Mode The EPI General-Purpose Mode is designed for high-speed clocked interfaces such as ones communicating with FPGAs and CPLDs. The high-speed clocked interfaces are different from the slower Host Bus interfaces, which have more relaxed timings that are compatible with established protocols like ones used to communicate with 8051 devices. Support of bus cycle framing and precisely controlled clocking are the additional features of the General-Purpose Mode that differentiate the General-Purpose Mode from the 8-bit and 16-bit Host Bus Modes. Framing allows multiple bus transactions to be grouped together with an output signal called FRAME. The slave device responding to the bus cycles may use this signal to recognize related words of data and to speed up their transfers. The frame lengths are programmable and may vary from 1 to 30 clocks, depending on the clocking mode used. Precise clocking is accomplished with a dedicated clock output pin (CLK). Devices responding the bus cycles can synchronize to CLK for faster transfers. The clock frequency can be precisely controlled through the Baud Rate Control block. This output clock can be gated or free-running. A gated approach uses a setup-time model in which the EPI clock controls when bus transactions are starting and stopping. A free-running EPI clock requires another method for determining when data is live, such as the frame pin or RD/WR strobes. These and numerous other aspects of the General-Purpose Mode are controlled through the General- Purpose Configuration Register and the General-Purpose Configuration2 Register. The clocking for the General-Purpose Mode is configured through the EPI Baud Register of the EPI Baud Rate Control block. See Figure 7-8 for a snapshot of the General-Purpose Mode registers, modes, and features. For more detailed maps of the General-Purpose Mode, see Table 7-4. 150 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 7-8. EPI General-Purpose Modes Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 151 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-4. EPI MODES – General-Purpose Mode (EPICFG/MODE = 0x0) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN General-Purpose General-Purpose General-Purpose General-Purpose Accessible by Accessible by (Available GPIOMUX_1 Signal Signal Signal Signal Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Muxing Choices for EPI) (D8, A20) (D16, A12) (D24, A4) (D30, No Addr) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 A0 D8 D8 D8 PE0_GPIO24 EPI0S9 A1 D9 D9 D9 PE1_GPIO25 EPI0S10 A2 D10 D10 D10 PH4_GPIO52 EPI0S11 A3 D11 D11 D11 PH5_GPIO53 EPI0S12 A4 D12 D12 D12 PF4_GPIO36 EPI0S13 A5 D13 D13 D13 PG0_GPIO40 EPI0S14 A6 D14 D14 D14 PG1_GPIO41 EPI0S15 A7 D15 D15 D15 PF5_GPIO37 EPI0S16 A8 A0 D16 D16 PJ0_GPIO56 EPI0S17 A9 A1 D17 D17 PJ1_GPIO57 EPI0S18 A10 A2 D18 D18 PJ2_GPIO58 EPI0S19 A11 A3 D19 D19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A12 A4 D29 D29 PD2_GPIO18 EPI0S21 A13 A5 D21 D21 PD3_GPIO19 EPI0S22 A14 A6 D22 D22 PB5_GPIO13 EPI0S23 A15 A7 D23 D23 PB4_GPIO12 EPI0S24 A16 A8 A0 D24 PE2_GPIO26 EPI0S25 A17 A9 A1 D25 PE3_GPIO27 EPI0S26 A18 A10 A2 D26 PH6_GPIO54 EPI0S27 A19/RDY A11/RDY A3/RDY D27 PH7_GPIO55 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 WR WR WR Df20;BACKGROUND-COLOR:#4ae2f7">28 PD5_GPIO21 PJ4_GPIO60 EPI0S29 RD RD RD D29 PD6_GPIO22 PJ5_GPIO61 EPI0S30 FRAME FRAME FRAME D30 PD7_GPIO23 PJ6_GPIO62 EPI0S31 CLK CLK CLK D31 PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 152 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.1.4.2 EPI SDRAM Mode The EPI SDRAM Mode combines high performance, low cost, and low pin utilization to access up to 512 megabits (Mb) of external memory. Main features of the EPI SDRAM interface are: ? Supports x16 (single data rate) SDRAM ? Supports low-cost SDRAMs up to 64 megabytes (MB) [or 512Mb] ? Includes automatic refresh and access to all banks, rows ? Includes Sleep/STANDBY Mode to keep contents active with minimal power drain ? Multiplexed address/data interface for reduced pin count See Figure 7-9 for a snapshot of the SDRAM Mode registers and supported memory sizes. For more detailed maps of the SDRAM Mode, see Table 7-5. Figure 7-9. EPI SDRAM Mode Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 153 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-5. EPI MODES – SDRAM Mode (EPICFG/MODE = 0x1) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN Accessible by (Available GPIOMUX_1 Accessible by Cf20;BACKGROUND-COLOR:#4ae2f7">28x Column/Row Address Data Cortex-M3 Muxing Choices for EPI) EPI0S0 A0 D0 PH3_GPIO51 EPI0S1 A1 D1 PH2_GPIO50 EPI0S2 A2 D2 PC4_GPIO68 EPI0S3 A3 D3 PC5_GPIO69 EPI0S4 A4 D4 PC6_GPIO70 EPI0S5 A5 D5 PC7_GPIO71 EPI0S6 A6 D6 PH0_GPIO48 EPI0S7 A7 D7 PH1_GPIO49 EPI0S8 A8 D8 PE0_GPIO24 EPI0S9 A9 D9 PE1_GPIO25 EPI0S10 A10 D10 PH4_GPIO52 EPI0S11 A11 D11 PH5_GPIO53 EPI0S12 A12 D12 PF4_GPIO36 EPI0S13 BA0 D13 PG0_GPIO40 EPI0S14 BA1 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S16 DQML PJ0_GPIO56 EPI0S17 DQMH PJ1_GPIO57 EPI0S18 CAS PJ2_GPIO58 EPI0S19 RAS PD4_GPIO20 PJ3_GPIO59 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 WE PD5_GPIO21 PJ4_GPIO60 EPI0S29 CS PD6_GPIO22 PJ5_GPIO61 EPI0S30 CKE PD7_GPIO23 PJ6_GPIO62 EPI0S31 CLK PG7_GPIO47 EPI0S20 x PD2_GPIO18 EPI0S21 x PD3_GPIO19 EPI0S22 x PB5_GPIO13 EPI0S23 x PB4_GPIO12 EPI0S24 x PE2_GPIO26 EPI0S25 x PE3_GPIO27 EPI0S26 x PH6_GPIO54 EPI0S27 x PH7_GPIO55 EPI0S32 x PF2_GPIO34 PC0_GPIO64 EPI0S33 x PF3_GPIO35 PC1_GPIO65 EPI0S34 x PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S35 x PE5_GPIO29 EPI0S36 x PB7_GPIO15 PC3_GPIO67 EPI0S37 x PB6_GPIO14 PC2_GPIO66 EPI0S38 x PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 x PG2_GPIO42 EPI0S40 x PG5_GPIO45 EPI0S41 x PG6_GPIO46 154 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.1.4.3 EPI Host Bus Mode There are two versions of the EPI Host Bus Mode: an 8-bit version (HB-8) and a 16-bit version (HB-16). Section 7.1.4.3.1 discusses the EPI 8-Bit Host Bus Mode. Section 7.1.4.3.2 discusses the EPI 16-Bit Host Bus Mode. 7.1.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode The 8-Bit Host Bus (HB-8) Mode uses fewer data pins than the 16-Bit Host Bus (HB-16) Mode; hence, more pins are available for address. The HB-8 Mode is also slower than the General-Purpose Mode in order to accommodate older logic. The HB-8 Mode is selected with the MODE field of EPI Configuration Register. Within the HB-8 Mode, two additional registers are used to select address/data muxing, chip selects, and other options. These registers are the HB-8 Configuration Register and the HB-8 Configuration2 Register. See Figure 7-10 for a snapshot of HB-8 registers, modes, and features. Figure 7-10. EPI 8-Bit Host Bus Mode 7.1.4.3.1.1 HB-8 Muxed Address/Data Mode The HB-8 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-8 Muxed Mode is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address signals, the HB-8 Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; and 1–4 CS (Chip Select) signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Muxed Mode, see Table 7- 6. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 155 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-6. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), Muxed (EPIHB16CFG/MODE = 0x0) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessible by Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1 Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 A8 A8 A8 A8 PE0_GPIO24 EPI0S9 A9 A9 A9 A9 PE1_GPIO25 EPI0S10 A10 A10 A10 A10 PH4_GPIO52 EPI0S11 A11 A11 A11 A11 PH5_GPIO53 EPI0S12 A12 A12 A12 A12 PF4_GPIO36 EPI0S13 A13 A13 A13 A13 PG0_GPIO40 EPI0S14 A14 A14 A14 A14 PG1_GPIO41 EPI0S15 A15 A15 A15 A15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 A24 PE2_GPIO26 EPI0S25 A25 A25 A25 A25 PE3_GPIO27 EPI0S26 A26 A26 A26 CS0 PH6_GPIO54 EPI0S27 A27 A27 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 156 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.1.4.3.1.2 HB-8 Non-Muxed Address/Data Mode The HB-8 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non- Muxed Mode has reduced address reach as compared to the Muxed Mode. The HB-8 Non-Muxed Mode is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address signals, the HB-8 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; and 1–4 CS (Chip Select) signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Non-Muxed Mode, see Table 7-7. Table 7-7. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), Non-Muxed (EPIHB16CFG/MODE = 0x1) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessible by Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1 Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 A0 A0 A0 A0 PE0_GPIO24 EPI0S9 A1 A1 A1 A1 PE1_GPIO25 EPI0S10 A2 A2 A2 A2 PH4_GPIO52 EPI0S11 A3 A3 A3 A3 PH5_GPIO53 EPI0S12 A4 A4 A4 A4 PF4_GPIO36 EPI0S13 A5 A5 A5 A5 PG0_GPIO40 EPI0S14 A6 A6 A6 A6 PG1_GPIO41 EPI0S15 A7 A7 A7 A7 PF5_GPIO37 EPI0S16 A8 A8 A8 A8 PJ0_GPIO56 EPI0S17 A9 A9 A9 A9 PJ1_GPIO57 EPI0S18 A10 A10 A10 A10 PJ2_GPIO58 EPI0S19 A11 A11 A11 A11 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A12 A12 A12 A12 PD2_GPIO18 EPI0S21 A13 A13 A13 A13 PD3_GPIO19 EPI0S22 A14 A14 A14 A14 PB5_GPIO13 EPI0S23 A15 A15 A15 A15 PB4_GPIO12 EPI0S24 A16 A16 A16 A16 PE2_GPIO26 EPI0S25 A17 A17 A17 A17 PE3_GPIO27 EPI0S26 A18 A18 A18 CS0 PH6_GPIO54 EPI0S27 A19 A19 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 157 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-7. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), Non-Muxed (EPIHB16CFG/MODE = 0x1) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessible by Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1 Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S34 x x x x PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 7.1.4.3.1.3 HB-8 FIFO Mode The HB-8 FIFO Mode uses 8 bits of data, removes ALE and address pins, and optionally adds external FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication devices (including USB2 devices), and some FPGA configuration (FIFO throughblock RAM). This FIFO Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can potentially block other CPU or DMA accesses. For more detailed maps of the HB-8 FIFO Mode, see Table 7-8. 158 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 7-8. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), FIFO Mode (EPIHB16CFG/MODE = 0x3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With One With Two Accessible by (Available GPIOMUX_1 Accessible by Cf20;BACKGROUND-COLOR:#4ae2f7">28x Chip Select Chip Selects Cortex-M3 Muxing Choices for EPI) (CSCFG = 0x1) (CSCFG = 0x2) EPI0S0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 PH1_GPIO49 EPI0S25 x CS1 PE3_GPIO27 EPI0S30 CS0 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S27 FFULL FFULL PH7_GPIO55 EPI0S26 FEMPTY FEMPTY PH6_GPIO54 EPI0S29 WR WR PD6_GPIO22 PJ5_GPIO61 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S8 x x PE0_GPIO24 EPI0S9 x x PE1_GPIO25 EPI0S10 x x PH4_GPIO52 EPI0S11 x x PH5_GPIO53 EPI0S12 x x PF4_GPIO36 EPI0S13 x x PG0_GPIO40 EPI0S14 x x PG1_GPIO41 EPI0S15 x x PF5_GPIO37 EPI0S16 x x PJ0_GPIO56 EPI0S17 x x PJ1_GPIO57 EPI0S18 x x PJ2_GPIO58 EPI0S19 x x PD4_GPIO20 PJ3_GPIO59 EPI0S20 x x PD2_GPIO18 EPI0S21 x x PD3_GPIO19 EPI0S22 x x PB5_GPIO13 EPI0S23 x x PB4_GPIO12 EPI0S24 x x PE2_GPIO26 EPI0S32 x x PF2_GPIO34 PC0_GPIO64 EPI0S31 x x PG7_GPIO47 EPI0S33 x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S35 x x PE5_GPIO29 EPI0S36 x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 x x PG2_GPIO42 EPI0S40 x x PG5_GPIO45 EPI0S41 x x PG6_GPIO46 Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 159 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.1.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode The 16-Bit Host Bus (HB-16) Mode uses fewer address pins than the 8-Bit Host Bus (HB-8) Mode; hence, more pins are available for data. The HB-16 Mode is also slower than the General-Purpose Mode in order to accommodate older logic. The HB-16 Mode is selected with the MODE field of EPI Configuration Register. Within the HB-16 Mode, two additional registers are used to select address/data muxing, byte selects, chip selects, and other options. These registers are the HB-16 Configuration Register and the HB-16 Configuration2 Register. See Figure 7-11 for a snapshot of HB-16 registers, modes, and features. Figure 7-11. EPI 16-Bit Host Bus Mode 160 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.1.4.3.2.1 HB-16 Muxed Address/Data Mode The HB-16 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-16 Muxed Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address signals, the HB-16 Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; 1–4 CS (Chip Select) signals to enable one of four external peripherals; and two BSEL (Byte Select) signals to accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16 Configuration2 Register. For more detailed maps of the HB-16 Muxed Mode without Byte Selects, see Table 7-9. For more detailed maps of the HB-16 Muxed Mode with Byte Selects, see Table 7-10. Table 7-9. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessible by Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1 Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 AD8 AD8 AD8 AD8 PE0_GPIO24 EPI0S9 AD9 AD9 AD9 AD9 PE1_GPIO25 EPI0S10 AD10 AD10 AD10 AD10 PH4_GPIO52 EPI0S11 AD11 AD11 AD11 AD11 PH5_GPIO53 EPI0S12 AD12 AD12 AD12 AD12 PF4_GPIO36 EPI0S13 AD13 AD13 AD13 AD13 PG0_GPIO40 EPI0S14 AD14 AD14 AD14 AD14 PG1_GPIO41 EPI0S15 AD15 AD15 AD15 AD15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 A24 PE2_GPIO26 EPI0S25 A25 A25 A25 A25 PE3_GPIO27 EPI0S26 A26 A26 A26 CS0 PH6_GPIO54 EPI0S27 A27 A27 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 161 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-9. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessible by Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1 Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Table 7-10. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessible by Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1 Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 AD8 AD8 AD8 AD8 PE0_GPIO24 EPI0S9 AD9 AD9 AD9 AD9 PE1_GPIO25 EPI0S10 AD10 AD10 AD10 AD10 PH4_GPIO52 EPI0S11 AD11 AD11 AD11 AD11 PH5_GPIO53 EPI0S12 AD12 AD12 AD12 AD12 PF4_GPIO36 EPI0S13 AD13 AD13 AD13 AD13 PG0_GPIO40 EPI0S14 AD14 AD14 AD14 AD14 PG1_GPIO41 EPI0S15 AD15 AD15 AD15 AD15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 BSEL0 PE2_GPIO26 EPI0S25 A25 A25 BSEL0 BSEL1 PE3_GPIO27 162 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 7-10. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessible by Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1 Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S26 BSEL0 BSEL0 BSEL1 CS0 PH6_GPIO54 EPI0S27 BSEL1 BSEL1 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 7.1.4.3.2.2 HB-16 Non-Muxed Address/Data Mode The HB-16 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non- Muxed Mode has reduced address reach as compared to the Muxed Mode. The HB-16 Non-Muxed Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address signals, the HB-16 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; 1–4 CS (Chip Select) signals to enable one of four external peripherals; and two BSEL (Byte Select) signals to accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16 Configuration2 Register. For Non-Muxed bus cycles, most of the CSCFG modes also support a RDY signal. The RDY input to EPI is used by an external peripheral to extend bus cycles when the peripheral needs more time to complete reading or writing of data. While most EPI modes use up to 32 pins, the Non-Muxed CSCFG modes with 3 and 4 Chip Selects use 10 additional pins to extend the address reach and the number of CS signals. For detailed maps of HB-16 Non-Muxed Modes without Byte Selects, see Table 7-11 and Table 7-12. For detailed maps of HB-16 Non-Muxed Modes with Byte Selects, see Table 7-13 and Table 7-14. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 163 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-11. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1 Accessible by Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cortex-M3 Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 D15 D15 PF5_GPIO37 EPI0S16 A0 A0 A0 A0 PJ0_GPIO56 EPI0S17 A1 A1 A1 A1 PJ1_GPIO57 EPI0S18 A2 A2 A2 A2 PJ2_GPIO58 EPI0S19 A3 A3 A3 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 A4 A4 A4 PD2_GPIO18 EPI0S21 A5 A5 A5 A5 PD3_GPIO19 EPI0S22 A6 A6 A6 A6 PB5_GPIO13 EPI0S23 A7 A7 A7 A7 PB4_GPIO12 EPI0S24 A8 A8 A8 A8 PE2_GPIO26 EPI0S25 A9 A9 A9 A9 PE3_GPIO27 EPI0S26 A10 A10 A10 CS0 PH6_GPIO54 EPI0S27 A11 A11 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x RDY RDY RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x x x x PG7_GPIO47 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 164 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 7-12. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE=0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7) EPI SIGNAL EPI SIGNAL EPI PORT NAME DEVICE PIN EPI PORT NAME DEVICE PIN FUNCTION FUNCTION With With Accessible Accessible Accessible Accessible Three (Available GPIOMUX_1 Four (Available GPIOMUX_1 by by by by Chip Selects Muxing Choices for EPI) Chip Selects Muxing Choices for EPI) Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x (CSCFG = 0x7) (CSCFG = 0x5) EPI0S0 D0 PH3_GPIO51 EPI0S0 D0 PH3_GPIO51 EPI0S1 D1 PH2_GPIO50 EPI0S1 D1 PH2_GPIO50 EPI0S2 D2 PC4_GPIO68 EPI0S2 D2 PC4_GPIO68 EPI0S3 D3 PC5_GPIO69 EPI0S3 D3 PC5_GPIO69 EPI0S4 D4 PC6_GPIO70 EPI0S4 D4 PC6_GPIO70 EPI0S5 D5 PC7_GPIO71 EPI0S5 D5 PC7_GPIO71 EPI0S6 D6 PH0_GPIO48 EPI0S6 D6 PH0_GPIO48 EPI0S7 D7 PH1_GPIO49 EPI0S7 D7 PH1_GPIO49 EPI0S8 D8 PE0_GPIO24 EPI0S8 D8 PE0_GPIO24 EPI0S9 D9 PE1_GPIO25 EPI0S9 D9 PE1_GPIO25 EPI0S10 D10 PH4_GPIO52 EPI0S10 D10 PH4_GPIO52 EPI0S11 D11 PH5_GPIO53 EPI0S11 D11 PH5_GPIO53 EPI0S12 D12 PF4_GPIO36 EPI0S12 D12 PF4_GPIO36 EPI0S13 D13 PG0_GPIO40 EPI0S13 D13 PG0_GPIO40 EPI0S14 D14 PG1_GPIO41 EPI0S14 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S15 D15 PF5_GPIO37 EPI0S16 A0 PJ0_GPIO56 EPI0S16 A0 PJ0_GPIO56 EPI0S17 A1 PJ1_GPIO57 EPI0S17 A1 PJ1_GPIO57 EPI0S18 A2 PJ2_GPIO58 EPI0S18 A2 PJ2_GPIO58 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 PD2_GPIO18 EPI0S20 A4 PD2_GPIO18 EPI0S21 A5 PD3_GPIO19 EPI0S21 A5 PD3_GPIO19 EPI0S22 A6 PB5_GPIO13 EPI0S22 A6 PB5_GPIO13 EPI0S23 A7 PB4_GPIO12 EPI0S23 A7 PB4_GPIO12 EPI0S24 A8 PE2_GPIO26 EPI0S24 A8 PE2_GPIO26 EPI0S25 A9 PE3_GPIO27 EPI0S25 A9 PE3_GPIO27 EPI0S26 A10 PH6_GPIO54 EPI0S26 A10 PH6_GPIO54 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S38 A13 PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S38 A13 PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 A14 PG2_GPIO42 EPI0S39 A14 PG2_GPIO42 EPI0S27 A15 PH7_GPIO55 EPI0S40 A15 PG5_GPIO45 EPI0S35 A16 PE5_GPIO29 EPI0S41 A16 PG6_GPIO46 EPI0S40 A17 PG5_GPIO45 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S41 A18 PG6_GPIO46 EPI0S27 CS1 PH7_GPIO55 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S34 CS2 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S34 CS2 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD PD5_GPIO21 PJ4_GPIO60 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x PG7_GPIO47 EPI0S31 x PG7_GPIO47 EPI0S35 x PE5_GPIO29 Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 165 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-13. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1 Accessible by Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cortex-M3 Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 D15 D15 PF5_GPIO37 EPI0S16 A0 A0 A0 A0 PJ0_GPIO56 EPI0S17 A1 A1 A1 A1 PJ1_GPIO57 EPI0S18 A2 A2 A2 A2 PJ2_GPIO58 EPI0S19 A3 A3 A3 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 A4 A4 A4 PD2_GPIO18 EPI0S21 A5 A5 A5 A5 PD3_GPIO19 EPI0S22 A6 A6 A6 A6 PB5_GPIO13 EPI0S23 A7 A7 A7 A7 PB4_GPIO12 EPI0S24 A8 A8 A8 BSEL0 PE2_GPIO26 EPI0S25 A9 A9 BSEL0 BSEL1 PE3_GPIO27 EPI0S26 BSEL0 BSEL0 BSEL1 CS0 PH6_GPIO54 EPI0S27 BSEL1 BSEL1 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x RDY RDY RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x x x x PG7_GPIO47 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 166 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 7-14. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7) EPI SIGNAL EPI SIGNAL EPI PORT NAME DEVICE PIN EPI PORT NAME DEVICE PIN FUNCTION FUNCTION With With Accessible Accessible Accessible Accessible Three (Available GPIOMUX_1 Four (Available GPIOMUX_1 by by by by Chip Selects Muxing Choices for EPI) Chip Selects Muxing Choices for EPI) Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Cortex-M3 Cf20;BACKGROUND-COLOR:#4ae2f7">28x (CSCFG = 0x7) (CSCFG = 0x5) EPI0S0 D0 PH3_GPIO51 EPI0S0 D0 PH3_GPIO51 EPI0S1 D1 PH2_GPIO50 EPI0S1 D1 PH2_GPIO50 EPI0S2 D2 PC4_GPIO68 EPI0S2 D2 PC4_GPIO68 EPI0S3 D3 PC5_GPIO69 EPI0S3 D3 PC5_GPIO69 EPI0S4 D4 PC6_GPIO70 EPI0S4 D4 PC6_GPIO70 EPI0S5 D5 PC7_GPIO71 EPI0S5 D5 PC7_GPIO71 EPI0S6 D6 PH0_GPIO48 EPI0S6 D6 PH0_GPIO48 EPI0S7 D7 PH1_GPIO49 EPI0S7 D7 PH1_GPIO49 EPI0S8 D8 PE0_GPIO24 EPI0S8 D8 PE0_GPIO24 EPI0S9 D9 PE1_GPIO25 EPI0S9 D9 PE1_GPIO25 EPI0S10 D10 PH4_GPIO52 EPI0S10 D10 PH4_GPIO52 EPI0S11 D11 PH5_GPIO53 EPI0S11 D11 PH5_GPIO53 EPI0S12 D12 PF4_GPIO36 EPI0S12 D12 PF4_GPIO36 EPI0S13 D13 PG0_GPIO40 EPI0S13 D13 PG0_GPIO40 EPI0S14 D14 PG1_GPIO41 EPI0S14 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S15 D15 PF5_GPIO37 EPI0S16 A0 PJ0_GPIO56 EPI0S16 A0 PJ0_GPIO56 EPI0S17 A1 PJ1_GPIO57 EPI0S17 A1 PJ1_GPIO57 EPI0S18 A2 PJ2_GPIO58 EPI0S18 A2 PJ2_GPIO58 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 PD2_GPIO18 EPI0S20 A4 PD2_GPIO18 EPI0S21 A5 PD3_GPIO19 EPI0S21 A5 PD3_GPIO19 EPI0S22 A6 PB5_GPIO13 EPI0S22 A6 PB5_GPIO13 EPI0S23 A7 PB4_GPIO12 EPI0S23 A7 PB4_GPIO12 EPI0S24 A8 PE2_GPIO26 EPI0S24 A8 PE2_GPIO26 EPI0S40 A9 PG5_GPIO45 EPI0S40 A9 PG5_GPIO45 EPI0S41 A10 PG6_GPIO46 EPI0S41 A10 PG6_GPIO46 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S38 A13 PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S38 A13 PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 A14 PG2_GPIO42 EPI0S39 A14 PG2_GPIO42 EPI0S27 A15 PH7_GPIO55 EPI0S25 BSEL0 PE3_GPIO27 EPI0S35 A16 PE5_GPIO29 EPI0S26 BSEL1 PH6_GPIO54 EPI0S25 BSEL0 PE3_GPIO27 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S26 BSEL1 PH6_GPIO54 EPI0S27 CS1 PH7_GPIO55 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S34 CS2 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S34 CS2 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD PD5_GPIO21 PJ4_GPIO60 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x PG7_GPIO47 EPI0S31 x PG7_GPIO47 EPI0S35 x PE5_GPIO29 Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 167 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.1.4.3.2.3 HB-16 FIFO Mode The HB-16 FIFO Mode uses 16 bits of data, removes ALE and address pins, and optionally adds external FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication devices (including USB2 devices), and some FPGA configuration (FIFO throughblock RAM). This FIFO Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can potentially block other CPU or DMA accesses. For detailed maps of the HB-16 FIFO Mode, see Table 7- 15. Table 7-15. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), FIFO Mode (EPIHB16CFG/MODE = 0x3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With One With Two Accessible by (Available GPIOMUX_1 Accessible by Cf20;BACKGROUND-COLOR:#4ae2f7">28x Chip Select Chip Selects Cortex-M3 Muxing Choices for EPI) (CSCFG = 0x1) (CSCFG = 0x2) EPI0S0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 PF5_GPIO37 EPI0S25 x CS1 PE3_GPIO27 EPI0S30 CS0 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S27 FFULL FFULL PH7_GPIO55 EPI0S26 FEMPTY FEMPTY PH6_GPIO54 EPI0S29 WR WR PD6_GPIO22 PJ5_GPIO61 EPI0Sf20;BACKGROUND-COLOR:#4ae2f7">28 RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x x PF2_GPIO34 PC0_GPIO64 EPI0S16 x x PJ0_GPIO56 EPI0S17 x x PJ1_GPIO57 EPI0S18 x x PJ2_GPIO58 EPI0S19 x x PD4_GPIO20 PJ3_GPIO59 EPI0S20 x x PD2_GPIO18 EPI0S21 x x PD3_GPIO19 EPI0S22 x x PB5_GPIO13 EPI0S23 x x PB4_GPIO12 EPI0S24 x x PE2_GPIO26 EPI0S31 x x PG7_GPIO47 168 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 7-15. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), FIFO Mode (EPIHB16CFG/MODE = 0x3) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With One With Two Accessible by (Available GPIOMUX_1 Accessible by Cf20;BACKGROUND-COLOR:#4ae2f7">28x Chip Select Chip Selects Cortex-M3 Muxing Choices for EPI) (CSCFG = 0x1) (CSCFG = 0x2) EPI0S33 x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S35 x x PE5_GPIO29 EPI0S36 x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x PF6_GPIO38 PE4_GPIOf20;BACKGROUND-COLOR:#4ae2f7">28 EPI0S39 x x PG2_GPIO42 EPI0S40 x x PG5_GPIO45 EPI0S41 x x PG6_GPIO46 7.1.4.4 EPI Electrical Data and Timing The signal names in Figure 7-12 through Figure 7-20 are defined in Table 7-16. Table 7-16. Signals in Figure 7-12 Through Figure 7-20 SIGNAL DESCRIPTION AD Address/Data Address Address output ALE Address latch enable BAD Bank Address/Data BSEL0, BSEL1 Byte select CAS Column address strobe CKE Clock enable CLK, Clock Clock Command Command signal CS Chip select Data Data signals DQMH Data mask high DQML Data mask low Frame Frame signal iRDY Ready input Muxed Address/Data Multiplexed Address/Data RAS Row address strobe RD/OE Read enable/Output enable WE, WR Write enable Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 169 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-17. EPI SDRAM Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 7-12, Figure 7-13, and Figure 7-14) NO. PARAMETER MIN MAX UNIT E1 tc(CK) Cycle time, SDRAM clock 20 ns E2 tw(CKH) Pulse duration, SDRAM clock high 10 ns E3 tw(CKL) Pulse duration, SDRAM clock low 10 ns E4 td(CK-OV) Delay time, clock to output valid –5 5 ns E5 td(CK-OIV) Delay time, clock to output invalid –5 5 ns E6 td(CK-OZ) Delay time, clock to output high-impedance –5 5 ns E7 tsu(AD-CK) Setup time, input before clock 10 ns E8 th(CK-AD) Hold time, input after clock 0 ns E9 tPU Power-up time 100 ?s E10 tpc Precharge time, all banks 20 ns E11 trf Autorefresh 66 ns E12 tMRD Program mode register 40 ns A. If CS is high at clock high time, all applied commands are NOP. B. The Mode register may be loaded prior to the autorefresh cycles if desired. C. JEDEC and PC100 specify three clocks. D. Outputs are ensured High-Z after command is issued. Figure 7-12. SDRAM Initialization and Load Mode Register Timing Figure 7-13. SDRAM Read Timing 170 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 7-14. SDRAM Write Timing Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 171 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-18. EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 7-15, Figure 7-16, Figure 7-17, and Figure 7-18) NO. PARAMETER MIN TYP MAX UNIT E16 td(WR-WDATAV) Delay time, WR to write data valid 5 ns EPI E17 td(WRIV-DATA) Delay time, WR invalid to data 2 clocks E18 td(CS-OV) Delay time, CS to output valid –5 5 ns E19 td(CS-OIV) Delay time, CS to output invalid –5 5 ns EPI E20 tw(STL) Pulse duration, WR/RD strobe low 2 clocks EPI E22 tw(ALEH) Pulse duration, ALE high 1 clocks EPI E23 tw(CSL) Pulse duration, CS low 4 clocks EPI E24 td(ALE-ST) Delay time, ALE rising to WR/RD strobe falling 2 clocks EPI E25 td(ALE-ADHZ) Delay time, ALE falling to Address/Data high-impedance 1 clocks Table 7-19. EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements(1) (see Figure 7-15 and Figure 7-17) NO. MIN MAX UNIT E14 tsu(RDATA) Setup time, read data 10 ns E15 th(RDATA) Hold time, read data 0 ns (1) Setup time for FEMPTY and FFULL signals from clock edge is 2 system clocks (MIN). A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only. Figure 7-15. Host-Bus 8/16 Mode Read Timing 172 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only. Figure 7-16. Host-Bus 8/16 Mode Write Timing A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only. Figure 7-17. Host-Bus 8/16 Mode Muxed Read Timing A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only. Figure 7-18. Host-Bus 8/16 Mode Muxed Write Timing Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 173 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-20. EPI General-Purpose Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 7-19) NO. PARAMETER MIN MAX UNIT E26 tw(CKH) Pulse duration, general-purpose clock high 10 ns E27 tw(CKL) Pulse duration, general-purpose clock low 10 ns E30 td(CK-OV) Delay time, falling clock edge to output valid –5 5 ns E31 td(CK-OIV) Delay time, falling clock edge to output invalid –5 5 ns E33 tc(CK) Cycle time, general-purpose clock 20 ns Table 7-21. EPI General-Purpose Interface Timing Requirements (see Figure 7-19 and Figure 7-20) NO. MIN MAX UNIT Ef20;BACKGROUND-COLOR:#4ae2f7">28 tsu(IN-CK) Setup time, input signal before rising clock edge 10 ns E29 th(CK-IN) Hold time, input signal after rising clock edge 0 ns E32 tsu(IRDY-CK) Setup time, iRDY assertion or de-assertion before falling clock edge 10 ns A. This figure illustrates accesses where the FRM50 bit is clear, the FRMCNT field is 0x0, the RD2CYC bit is clear, and the WR2CYC bit is clear. Figure 7-19. General-Purpose Mode Read and Write Timing Figure 7-20. General-Purpose Mode iRDY Timing 174 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.2 Master Subsystem Peripherals Master Subsystem peripherals are located on the APB Bus and AHB Bus, and are accessible from the Cortex-M3 CPU/?DMA. The AHB peripherals include EPI, USB, and two CAN modules. The APB peripherals include EMAC, two I2 Cs, five UARTs, four SSIs, four GPTIMERs, two WDOGs, NMI WDOG, and a ?CRC module (Cyclic Redundancy Check). The Cortex-M3 CPU/?DMA also have access to Analog (Result Registers only) and Shared peripherals (see Section 7.1). For detailed information on the processor peripherals, see the Concerto Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Technical Reference Manual (literature number SPRUH22). 7.2.1 Synchronous Serial Interface This device has four SSI modules. Each SSI has a Master or Slave interface for synchronous serial communication with peripheral devices that have Texas Instruments? SSIs, SPI, MICROWIRE, or Freescale? serial format. The SSI peripheral performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO memories, allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. The SSI also supports ?DMA transfers. The transmit and receive FIFOs can be programmed as destination/source addresses in the ?DMA module. An ?DMA operation is enabled by setting the appropriate bit or bits in the SSIDMACTL register. Figure 7-21 shows the SSI peripheral. 7.2.1.1 Bit Rate Generation The SSI includes a programmable bit-rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing-down the input clock (SysClk). The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register. The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register. The frequency of the output clock SSIClk is defined by: SSIClk = SysClk / [CPSDVSR * (1 + SCR)] NOTE For master mode, the system clock must be at least four times faster than SSIClk, with the restriction that SSIClk cannot be faster than 25 MHz. For slave mode, the system clock must be at least 12 times faster than SSIClk. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 175 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 7-21. SSI 176 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.2.1.2 Transmit FIFO The transmit FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. The CPU writes data to the FIFO through the SSI Data (SSIDR) register, and data is stored in the FIFO until the data is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty and the master initiates a transaction, the slave transmits the 8th most recent value in the transmit FIFO. If less than eight values have been written to the transmit FIFO since the SSI module clock was enabled using the SSI bit in the RGCG1 register, then "0" is transmitted. Care should be taken to ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt or an ?DMA request when the FIFO is empty. 7.2.1.3 Receive FIFO The receive FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 7.2.1.4 Interrupts The SSI can generate interrupts when the following conditions are observed: ? Transmit FIFO service (when the transmit FIFO is half full or less) ? Receive FIFO service (when the receive FIFO is half full or more) ? Receive FIFO time-out ? Receive FIFO overrun ? End of transmission All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI generates a single interrupt request to the controller regardless of the number of active interrupts. Each of the four individual maskable interrupts can be masked by clearing the appropriate bit in the SSI Interrupt Mask (SSIIM) register. Setting the appropriate mask bit enables the interrupt. The individual outputs, along with a combined interrupt output, allow the use of either a global interrupt service routine or modular device drivers to handle interrupts. The transmit and receive dynamic data-flow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers. The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not SSIClk is currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If the RX FIFO is emptied before 32 clocks have passed, the time-out period is reset. As a result, the ISR should clear the Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing a "1" to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared so late that the ISR returns before the interrupt is actually cleared, or the ISR may be reactivated unnecessarily. The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely. This interrupt can be used to indicate when it is safe to turn off the SSI module clock or enter sleep mode. In addition, because transmitted data and received data complete at exactly the same time, the interrupt can also indicate that read data is ready immediately, without waiting for the receive FIFO time-out period to complete. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 177 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.2.1.5 Frame Formats Each data frame is between 4 bits and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. Three basic frame types can be selected: ? Texas Instruments Synchronous Serial ? Freescale SPI ? MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive time-out indication that occurs when the receive FIFO still contains data after a time-out period. 178 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.2.2 Universal Asynchronous Receiver/Transmitter This device has five UART modules. The CPU accesses data, control, and status information. The UART also supports ?DMA transfers. Each UART performs functions of parallel-to-serial and serial-to-parallel conversions. Each of the five UART modules is similar in functionality to a 16C550 UART, but is not register-compatible. The UART is configured for transmit and receive via the TXE bit and the RXE bit, respectively, of the UART Control (UARTCTL) register. Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. Figure 7-22 shows the UART peripheral. 7.2.2.1 Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register, and the 6- bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register. The baud rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD, and BRDF is the fractional part, separated by a decimal place). BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate) where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE in UARTCTL is clear) or 8 (if HSE is set). The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying this fractional part by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 8x or 16x the baud rate [referred to as Baud8 and Baud16, depending on the setting of the HSE bit (bit 5 in UARTCTL)]. This reference clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register, the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 179 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 7-22. UART 180 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.2.2.2 Transmit and Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. 7.2.2.3 Data Transmission and Reception Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, a data frame starts transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx signal is continuously "1"), and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 or the fourth cycle of Baud8, depending on the setting of the HSE bit (bit 5 in UARTCTL). The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE clear) or the fourth cycle of Baud 8 (HSE set), otherwise the start bit is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, one bit period later), according to the programmed length of the data characters and value of the HSE bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO along with any error bits associated with that word. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 181 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.2.2.4 Interrupts The UART can generate interrupts when the following conditions are observed: ? Overrun Error ? Break Error ? Parity Error ? Framing Error ? Receive Time-out ? Transmit (when the condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer) ? Receive (when the condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register. The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM) register by setting the corresponding IM bits. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register. Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a "1" to the corresponding bit in the UART Interrupt Clear (UARTICR) register. The receive time-out interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive time-out interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a "1" is written to the corresponding bit in the UARTICR register. 182 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.2.3 Cortex-M3 Inter-Integrated Circuit This device has two Cortex-M3 I2 C peripherals. The Cortex-M3 I2 C bus provides bidirectional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2 C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2 C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The microcontroller includes two I2 C modules, providing the ability to interact (both transmit and receive) with other I2 C devices on the bus. The two Cortex-M3 I2 C modules include the following features: ? Devices on the I2 C bus can be designated as either a master or a slave – Supports both transmitting and receiving data as either a master or a slave – Supports simultaneous master and slave operation ? Four I2 C modes – Master transmit – Master receive – Slave transmit – Slave receive ? Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) ? Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected ? Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode Figure 7-23 shows the Cortex-M3 I2 C peripheral. 7.2.3.1 Functional Overview Each I2 C module comprises both master and slave functions. For proper operation, the SDA and SCL pins must be configured as open-drain signals. The I2 C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL. SDA is the bidirectional serial data line and SCL is the bidirectional serial clock line. The bus is considered idle when both lines are high. Every transaction on the I2 C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, the receiver can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL. 7.2.3.2 Available Speed Modes The I2 C bus can run in either standard mode (100 Kbps) or fast mode (400 Kbps). The selected mode should match the speed of the other I2 C devices on the bus. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 183 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 7-23. I2 C (Cortex-M3) 184 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.2.3.3 I2 C Electrical Data and Timing Table 7-22. I2 C Timing TEST CONDITIONS MIN MAX UNIT fSCL SCL clock frequency I2 C clock module frequency is between 400 kHz 7 MHz and 12 MHz and I2 C prescaler and clock divider registers are configured appropriately vil Low level input voltage 0.3 VDDIO V Vih High level input voltage 0.7 VDDIO V Vhys Input hysteresis 0.05 VDDIO V Vol Low level output voltage 3 mA sink current 0 0.4 V tLOW Low period of SCL clock I2 C clock module frequency is between 1.3 μs 7 MHz and 12 MHz and I2 C prescaler and clock divider registers are configured appropriately tHIGH High period of SCL clock I2 C clock module frequency is between 0.6 μs 7 MHz and 12 MHz and I2 C prescaler and clock divider registers are configured appropriately lI Input current with an input voltage –10 10 μA between 0.1 VDDIO and 0.9 VDDIO MAX Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 185 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.2.4 Cortex-M3 Controller Area Network This device has two Cortex-M3 CAN peripherals. CAN is a serial communications protocol that efficiently supports distributed real-time control with a high level of security. The CAN module supports bit rates up to 1 Mbit/s and is compliant with the CAN 2.0B protocol specification. CAN implements the following features: ? CAN protocol version 2.0 part A, B ? Bit rates up to 1 Mbit/s ? Multiple clock sources ? 32 message objects ? Individual identifier mask for each message object ? Programmable FIFO mode for message objects ? Programmable loop-back modes for self-test operation ? Suspend mode for debug support ? Software module reset ? Automatic bus on after Bus-Off state by a programmable 32-bit timer ? Message RAM parity check mechanism ? Two interrupt lines ? Global power down and wakeup support Figure 7-24 shows the Cortex-M3 CAN peripheral. 7.2.4.1 Functional Overview CAN performs CAN protocol communication according to ISO 11898-1 (identical to Bosch? CAN protocol specification 2.0 A, B). The bit rate can be programmed to values up to 1 Mbit/s. Additional transceiver hardware is required for the connection to the physical layer (CAN bus). For communication on a CAN network, individual message objects can be configured. The message objects and identifier masks are stored in the Message RAM. All functions concerning the handling of messages are implemented in the message handler. Those functions are: acceptance filtering, the transfer of messages between the CAN Core and the Message RAM, and the handling of transmission requests. The register set of the CAN is accessible directly by the CPU via the module interface. These registers are used to control/configure the CAN Core and the message handler, and to access the message RAM. 186 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 7-24. CAN (Cortex-M3) Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 187 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.2.5 Cortex-M3 Universal Serial Bus Controller This device has one Cortex-M3 USB controller. The USB controller operates as a full-speed or low-speed function controller during point-to-point communications with the USB Host, Device, or OTG functions. The controller complies with the USB 2.0 standard, which includes SUSPEND and RESUME signaling. Thirty- two endpoints, which comprised of 2 hardwired endpoints for control transfers (one endpoint for IN and one endpoint for OUT) and 30 endpoints defined by firmware, along with a dynamic sizable FIFO, support multiple packet queuing. DMA access to the FIFO allows minimal interference from system software. Software-controlled connect and disconnect allow flexibility during USB device start-up. The controller complies with the OTG standard's Session Request Protocol (SRP) and Host Negotiation Protocol (HNP). The USB controller includes the following features: ? Complies with USB-IF certification standards ? USB 2.0 full-speed (12-Mbps) and low-speed (1.5-Mbps) operation ? Integrated PHY ? Four transfer types: Control, Interrupt, Bulk, and Isochronous ? 32 endpoints: – One dedicated control IN endpoint and one dedicated control OUT endpoint – 15 configurable IN endpoints and 15 configurable OUT endpoints ? 4KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size ? VBUS droop and valid ID detection and interrupt ? Efficient transfers using DMA: – Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints – Channel requests asserted when FIFO contains required amount of data ? Electrical specifications are compliant with the USB Specification Rev. 2.0 (full-speed and low-speed support) and the On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0. Some components of the USB system are integrated within the Concerto microcontroller and are specific to its design. Figure 7-25 shows the USB peripheral. 7.2.5.1 Functional Description The USB controller provides full OTG negotiation by supporting both the SRP and the HNP. The SRP allows devices on the B side of a cable to request the A-side devices' turn on VBUS. The HNP is used after the initial session request protocol has powered the bus and provides a method to determine which end of the cable will act as the Host controller. When the device is connected to non-OTG peripherals or devices, the controller can detect which cable end was used and provides a register to indicate if the controller should act as the Host controller or the Device controller. This indication and the mode of operation are handled automatically by the USB controller. This autodetection allows the system to use a single A/B connector instead of having both A and B connectors in the system, and supports full OTG negotiations with other OTG devices. In addition, the USB controller provides support for connecting to non-OTG peripherals or Host controllers. The USB controller can be configured to act as either a dedicated Host or Device, in which case, the USB0VBUS and USB0ID signals can be used as GPIOs. However, when the USB controller is acting as a self-powered Device, a GPIO input must be connected to VBUS and configured to generate an interrupt when the VBUS level drops. This interrupt is used to disable the pullup resistor on the USB0DP signal. NOTE When the USB is used, the system clock frequency (SYSCLK) must be at least 20 MHz. 188 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 7-25. USB Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 189 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.2.6 Cortex-M3 Ethernet Media Access Controller The Cortex-M3 EMAC conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE- TX standards. This device has one Ethernet Media Access Controller. The EMAC module has the following features: ? Conforms to the IEEE 802.3-2002 specification – 10BASE-T/100BASE-TX IEEE-802.3 compliant ? Multiple operational modes – Full- and half-duplex 100-Mbps – Full- and half-duplex 10-Mbps – Power-saving and power-down modes ? Highly configurable: – Programmable MAC address – Promiscuous mode support – CRC error-rejection control – User-configurable interrupts ? IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets ? Efficient transfers using the Micro Direct Memory Access Controller (?DMA) – Separate channels for transmit and receive – Receive channel request asserted on packet receipt – Transmit channel request asserted on empty transmit FIFO Figure 7-26 shows the EMAC peripheral. 7.2.6.1 Functional Overview The Ethernet Controller is functionally divided into two layers: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. The MAC resides inside the device, and the PHY outside of the device. These layers correspond to the OSI model layers 2 and 1, respectively. The CPU accesses the Ethernet Controller via the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC layer also provides the interface to the external PHY layer via an internal Media Independent Interface (MII). The PHY layer communicates with the Ethernet bus. 190 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 7-26. EMAC Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 191 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.2.6.2 MII Signals The individual EMAC and Management Data Input/Output (MDIO) signals for the MII interface are summarized in Table 7-23. Table 7-23. EMAC and MDIO Signals for MII Interface SIGNAL TYPE(1) DESCRIPTION Transmit clock. The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MIITXD and MIITXEN signals are tied to this clock. The clock is MIITXCK I generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps operation. MIITXER O This pin is always driven low from the MAC controller on the device. Transmit data. The transmit data pins are a collection of four data signals comprising 4 bits MIITXD[3-0] O of data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MIITXCLK and are valid only when MIITXEN is asserted. Transmit enable. The transmit enable signal indicates that the MIITXD pins are generating MIITXEN O nibble data for use by the PHY. MIITXEN is driven synchronously to MIITXCLK. Collision detected. In half-duplex operation, the MIICOL pin is asserted by the PHY when the PHY detects a collision on the network. The MIICOL pin remains asserted while the collision condition persists. This signal is not necessarily synchronous to MIITXCLK or MIIRXCLK. In MIICOL I full-duplex operation, the MIICOL pin is used for hardware transmit flow control. Asserting the MIICOL pin will stop packet transmissions; packets in the process of being transmitted when MIICOL is asserted will complete transmission. The MIICOL pin should be held low if hardware transmit flow control is not used. Carrier sense. In half-duplex operation, the MIICRS pin is asserted by the PHY when the network is not idle in either transmit or receive. The pin is deasserted when both transmit MIICRS I and receive are idle. This signal is not necessarily synchronous to MIITXCLK or MIIRXCLK. In full-duplex operation, the MIICRS pin should be held low. Receive clock. The receive clock is a continuous clock that provides the timing reference for receive operations. The MIIRXD, MIIRXDV, and MIIRXER signals are tied to this clock. The MIIRXCK I clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100- Mbps operation. Receive data. The receive data pins are a collection of four data signals comprising 4 bits of MIIRXD[3-0] I data. MRDX0 is the least-significant bit. The signals are synchronized by MIIRXCLK and are valid only when MIIRXDV is asserted. Receive data valid. The receive data valid signal indicates that the MIIRXD pins are MIIRXDV I generating nibble data for use by the EMAC. MIIRXDV is driven synchronously to MIIRXCLK. Receive error. The receive error signal is asserted for one or more MIIRXCLK periods to MIIRXER I indicate that an error was detected in the received frame. The MIIRXER signal being asserted is meaningful only during data reception when MIIRXDV is active. Management data clock. The MDIO data clock is sourced by the MDIO module on the system. MDIO_CK is used to synchronize MDIO data access operations done on the MDIO MDIO_CK O pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO Control Register (CONTROL). Management data input output. The MDIO data pin drives PHY management data into and out of the PHY by way of an access frame that consists of start-of-frame, read/write MDIO_D I/O indication, PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but the data bit cycles, at which time the pin is an input for read operations. (1) I = Input, O = Output, I/O = Input/Output 192 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.2.6.3 EMAC Electrical Data and Timing Table 7-24. Timing Requirements for MIITXCK (see Figure 7-27) 100 Mbps 10 Mbps NO. UNIT MIN MAX MIN MAX Cycle time, MIITXCK (25 MHz) 40 40 1 tc(TXCK) ns Cycle time, MIITXCK (2.5 MHz) 400 400 2 tw(TXCKH) Pulse duration, MIITXCK high 16 24 196 204 ns 3 tw(TXCKL) Pulse duration, MIITXCK low 16 24 196 204 ns Figure 7-27. 100/10Mb/s MII Transmit Clock Timing Table 7-25. Timing Requirements for MIIRXCK (see Figure 7-f20;BACKGROUND-COLOR:#4ae2f7">28) 100 Mbps 10 Mbps NO. UNIT MIN MAX MIN MAX Cycle time, MIIRXCK (25 MHz) 40 40 1 tc(RXCK) ns Cycle time, MIIRXCK (2.5 MHz) 400 400 2 tw(RXCKH) Pulse duration, MIIRXCK high 16 24 196 204 ns 3 tw(RXCKL) Pulse duration, MIIRXCK low 16 24 196 204 ns Figure 7-f20;BACKGROUND-COLOR:#4ae2f7">28. 100/10Mb/s MII Receive Clock Timing Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 193 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-26. Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for EMAC MII Transmit (see Figure 7-29) NO. PARAMETER MIN MAX UNIT 1 td(TXCKH-MTXDV) Delay time, MIITXCK high to transmit selected signals valid 5 25 ns Figure 7-29. 100/10Mb/s MII Transmit Timing Table 7-27. Timing Requirements for EMAC MII Receive (see Figure 7-30) NO. MIN NOM MAX UNIT 1 tsu(MRXDV-RXCKH) Setup time, receive selected signals valid before MIIRXCK high 8 ns 2 th(RXCKH-MRXDV) Hold time, receive selected signals valid after MIIRXCK high 7 ns Figure 7-30. 100/10Mb/s MII Receive Timing 194 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.2.6.4 MDIO Electrical Data and Timing Table 7-f20;BACKGROUND-COLOR:#4ae2f7">28. Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO_CK (see Figure 7-31) NO. PARAMETER MIN MAX UNIT 1 tc(MCK) Cycle time, MDIO_CK (2.5 MHz) 400 400 ns 2 tw(MCKH) Pulse duration, MDIO_CK high 196 204 ns 3 tw(MCKL) Pulse duration, MDIO_CK low 196 204 ns Figure 7-31. MII Serial Management Timing Table 7-29. Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO as Output (see Figure 7-32) NO. PARAMETER MIN MAX UNIT 1 td(MCKH-MDV) Delay time, MDIO_CK high to MDIO_D valid 5 25 ns Figure 7-32. MII Serial Management Timing – MDIO as Output Table 7-30. Timing Requirements for MDIO as Input (see Figure 7-33) NO. MIN NOM MAX UNIT 4 tsu(MDV-MCKH) Setup time, MDIO_D valid before MDIO_CK high 20 ns 5 th(MCKH-MDV) Hold time, MDIO_D valid after MDIO_CK high 7 ns Figure 7-33. MII Serial Management Timing – MDIO as Input Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 195 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.3 Control Subsystem Peripherals Control Subsystem peripherals are accessible from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU via the Cf20;BACKGROUND-COLOR:#4ae2f7">28x Memory Bus, and from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA via the Cf20;BACKGROUND-COLOR:#4ae2f7">28x DMA Bus. They include one NMI Watchdog, three Timers, four Serial Port Peripherals (SCI, SPI, McBSP, I2 C), and three types of Control Peripherals (ePWM, eQEP, eCAP). Additionally, the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU/DMA also have access to the EPI, and to Analog and Shared peripherals (see Section 7.1). For detailed information on the processor peripherals, see the Concerto Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Technical Reference Manual (literature number SPRUH22). 7.3.1 High-Resolution PWM and Enhanced PWM Modules There are nine PWM modules in the Concerto device. Eight of these are of the HRPWM type with high- resolution control on both A and B signal outputs, and one is of the ePWM type. The HRPWM modules have all the features of the ePWM plus they offer significantly higher PWM resolution (time granularity on the order of 150 ps). Figure 7-34 shows the eight HRPWM modules (PWM 1–8) and one ePWM module (PWM 9). The synchronization inputs to the PWM modules include the SYNCI signal from the GPTRIP1 output of GPIO_MUX1, and the TBCLKSYNC signal from the CPCLKCR0 register. Synchronization output SYNCO1 comes from the ePWM1 module and is stretched by 8 HSPCLK cycles before entering GPIO_MUX1. There are two groups of trip signal inputs to PWM modules. TRIP1–15 inputs come from GPTRIP1–12 (from GPIO_MUX1), ECCDBLERR signal (from Cf20;BACKGROUND-COLOR:#4ae2f7">28x Local and Shared RAM), and PIEERR signal from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU. TZ1–6 (Trip Zone) inputs come from GPTRIP 1–3 (from GPIO_MUX1), EQEPERR (from the eQEP peripheral), CLOCKFAIL (from M3 CLOCKS), and EMUSTOP (from the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU). There are 9 SOCA PWM outputs and 9 SOCB PWM outputs—a pair from each PWM module. The 9 SOCA outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering GPIO_MUX1 as a single SOCAO signal. The 9 SOCB outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering GPIO_MUX1 as a single SOCBO signal. The 18 SOCA/B outputs from PWM1–PWM9 also go to the Analog Subsystem, where they can be selected to become conversion triggers to ADC modules. The nine PWM modules also drive two other sets of outputs which can interrupt the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU via the Cf20;BACKGROUND-COLOR:#4ae2f7">28x PIE block. These are nine EPWMINT interrupts and nine EPWMTZINT trip-zone interrupts. See Figure 7-35 for the internal structure of the HRPWM and ePWM modules. The green-colored blocks are common to both ePWM and HRPWM modules, but only the HRPWMs have the grey-colored hi-resolution blocks. 196 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 7-34. PWM, eCAP, eQEP Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 197 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 7-35. Internal Structure of PWM 198 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.3.1.1 HRPWM Electrical Data and Timing Table 7-31 shows the high-resolution PWM switching characteristics. Table 7-31. High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz) PARAMETER MIN TYP MAX UNIT Micro Edge Positioning (MEP) step size(1) 150 310 ps (1) Maximum MEP step size is based on worst-case process, maximum temperature and minimum voltage. MEP step size will increase with low voltage and high temperature and decrease with voltage and cold temperature. Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per SYSCLKOUT period dynamically while the HRPWM is in operation. 7.3.1.2 ePWM Electrical Data and Timing Table 7-32 shows the PWM timing requirements and Table 7-33 shows the PWM switching characteristics. Table 7-32. ePWM Timing Requirements(1) MIN MAX UNIT tw(SYCIN) Sync input pulse width Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles With input qualifier 1tc(SCO) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-37. Table 7-33. ePWM Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tw(PWM) Pulse duration, PWMx output high/low 20 ns tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles td(PWM)tza Delay time, trip input active to PWM forced high no pin load 25 ns Delay time, trip input active to PWM forced low td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 199 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.3.1.2.1 Trip-Zone Input Timing Table 7-34. Trip-Zone Input Timing Requirements(1) MIN MAX UNIT tw(TZ) Pulse duration, TZx input low Asynchronous 1tc(SCO) cycles Synchronous 2tc(SCO) cycles With input qualifier 1tc(SCO) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-37. A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6 B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software. Figure 7-36. PWM Hi-Z Characteristics 200 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.3.2 Enhanced Capture Module There are six identical eCAP modules in Concerto devices: eCAP1, 2, 3, 4, 5, and 6. Each eCAP module represents one complete capture channel. Its main function is to accurately capture the timings of external events. One can also use eCAP modules for PWM, when they are not being used for input captures. This secondary function is selected by flipping the CAP/APWM bit of the ECCTL2 Register. For PWM function, the counter operates in count-up mode, providing a time base for asymmetrical pulse width (PWM) waveforms. The CAP1 and CAP2 registers become the period and compare registers, respectively; while the CAP3 and CAP4 registers become the shadow registers of the main period and capture registers, respectively. The left side of Figure 7-37 shows internal components associated with the capture block, and the right side depicts the PWM block. The two blocks share a set of four registers that are used in both Capture and PWM modes. Other components include the Counter block that uses the SYNCIN and SYNCOUT ports to synchronize with other modules; and the Interrupt Trigger and Flag Control block that sends Capture, PWM, and Counter events to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x PIE block via the ECAPxINT output. There are six ECAPxINT interrupts—one for each eCAP module. The eCAP peripherals are clocked by Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK, and its registers are accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU. This peripheral clock can be enabled or disabled by flipping a bit in one of the system control registers. 7.3.2.1 eCAP Electrical Data and Timing Table 7-35 shows the eCAP timing requirement and Table 7-36 shows the eCAP switching characteristics. Table 7-35. eCAP Timing Requirement(1) MIN MAX UNIT tw(CAP) Capture input pulse width Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles With input qualifier 1tc(SCO) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-37. Table 7-36. eCAP Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tw(APWM) Pulse duration, APWMx output high/low 20 ns Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 201 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 7-37. eCAP 202 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.3.3 Enhanced Quadrature Encoder Pulse Module The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position, direction, and speed information from rotating machines used in high-performance motion and position- control systems. There are three Type 0 eQEP modules in each Concerto device. Each eQEP peripheral comprises five major functional blocks: Quadrature Capture Unit (QCAP), Position Counter/Control Unit (PCCU), Quadrature Decoder (QDU), Unit Time Base for speed and frequency measurement (UTIME), and Watchdog timer for detecting stalls (QWDOG). The Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU controls and communicates with these modules through a set of associated registers (see Figure 7-38). The eQEP peripherals are clocked by Cf20;BACKGROUND-COLOR:#4ae2f7">28SYSCLK, and its registers are accessible by the Cf20;BACKGROUND-COLOR:#4ae2f7">28x CPU. This peripheral clock can be enabled or disabled by flipping a bit in one of the system control registers. Each eQEP peripheral connects through the GPIO_MUX1 block to four device pins. Two of the four pins are always inputs, while the other two can be inputs or outputs, depending on the operating mode. The PCCU block of each eQEP also drives one interrupt to the Cf20;BACKGROUND-COLOR:#4ae2f7">28x PIE. There is a total of three EQEPxINT interrupts—one from each of the three eQEP modules. 7.3.3.1 eQEP Electrical Data and Timing Table 7-37 shows the eQEP timing requirement and Table 7-38 shows the eQEP switching characteristics. Table 7-37. eQEP Timing Requirements(1) MIN MAX UNIT tw(QEPP) QEP input period Asynchronous(2) /synchronous 2tc(SCO) cycles With input qualifier 2[1tc(SCO) + tw(IQSW)] cycles tw(INDEXH) QEP Index Input High time Asynchronous(2) /synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles tw(INDEXL) QEP Index Input Low time Asynchronous(2) /synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles tw(STROBH) QEP Strobe High time Asynchronous(2) /synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles tw(STROBL) QEP Strobe Input Low time Asynchronous(2) /synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-37. (2) Refer to the Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Concerto MCU Silicon Errata (literature number SPRZ357) for limitations in the asynchronous mode. Table 7-38. eQEP Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync 6tc(SCO) cycles output Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 203 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 7-38. eQEP 204 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.3.4 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Inter-Integrated Circuit Module This device has one Cf20;BACKGROUND-COLOR:#4ae2f7">28x I2 C peripheral. The I2 C provides an interface between a Concerto device and devices compliant with the Philips? I2 C-Bus Specification Version 2.1 and connected by way of an I2 C bus. External components attached to this 2-wire serial bus can transmit 1-bit to 8-bit data to and receive 1-bit to 8-bit data from the device through the I2 C module. NOTE A unit of data transmitted or received by the I2 C module can have fewer than 8 bits; however, for convenience, a unit of data is called a data byte in this section. The number of bits in a data byte is selectable via the BC bits of the mode register, I2CMDR. The I2 C module has the following features: ? Compliance with the Philips I2 C-Bus Specification Version 2.1: – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit-and-receive and receive-and-transmit mode – Data transfer rate of from 10 Kbps up to 400 Kbps (I2 C Fast-mode rate) ? One 4-word receive FIFO and one 4-word transmit FIFO ? One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions: – Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received – Arbitration lost – Stop condition detected – Addressed as slave ? An additional interrupt that can be used by the CPU when in FIFO mode ? Module enable or disable capability ? Free data format mode The I2 C module does not support: ? High-speed mode (Hs-mode) ? CBUS-compatibility mode Figure 7-39 shows the Cf20;BACKGROUND-COLOR:#4ae2f7">28x I2 C peripheral. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 205 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 7-39. I2 C (Cf20;BACKGROUND-COLOR:#4ae2f7">28x) 206 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.3.4.1 Functional Overview Each device connected to an I2 C Bus is recognized by a unique address. Each device can operate as either a transmitter or a receiver, depending on the function of the device. A device connected to the I2 C Bus can also be considered as the master or the slave when performing data transfers. A master device is the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer. During this transfer, any device addressed by this master is considered a slave. The I2 C module supports the multi-master mode, in which one or more devices capable of controlling an I2 C Bus can be connected to the same I2 C Bus. For data communication, the I2 C module has a serial data pin (SDA) and a serial clock pin (SCL). These two pins carry information between the Cf20;BACKGROUND-COLOR:#4ae2f7">28x device and other devices connected to the I2 C Bus. The SDA and SCL pins both are bidirectional. They each must be connected to a positive supply voltage using a pullup resistor. When the bus is free, both pins are high. The driver of these two pins has an open-drain configuration to perform the required wired-AND function. There are two major transfer techniques: 1. Standard Mode: Send exactly n data values, where n is a value you program in an I2 C module register. 2. Repeat Mode: Keep sending data values until you use software to initiate a STOP condition or a new START condition. The I2 C module consists of the following primary blocks: ? A serial interface: one data pin (SDA) and one clock pin (SCL) ? Data registers and FIFOs to temporarily hold receive data and transmit data traveling between the SDA pin and the CPU ? Control and status registers ? A peripheral bus interface to enable the CPU to access the I2 C module registers and FIFOs. 7.3.4.2 Clock Generation The device clock generator receives a signal from an external clock source and produces an I2 C input clock with a programmed frequency. The I2 C input clock is equivalent to the CPU clock and is then divided twice more inside the I2 C module to produce the module clock and the master clock. 7.3.4.3 I2 C Electrical Data and Timing Table 7-39. I2 C Timing TEST CONDITIONS MIN MAX UNIT fSCL SCL clock frequency I2 C clock module frequency is between 400 kHz 7 MHz and 12 MHz and I2 C prescaler and clock divider registers are configured appropriately vil Low level input voltage 0.3 VDDIO V Vih High level input voltage 0.7 VDDIO V Vhys Input hysteresis 0.05 VDDIO V Vol Low level output voltage 3 mA sink current 0 0.4 V tLOW Low period of SCL clock I2 C clock module frequency is between 1.3 μs 7 MHz and 12 MHz and I2 C prescaler and clock divider registers are configured appropriately tHIGH High period of SCL clock I2 C clock module frequency is between 0.6 μs 7 MHz and 12 MHz and I2 C prescaler and clock divider registers are configured appropriately lI Input current with an input voltage –10 10 μA between 0.1 VDDIO and 0.9 VDDIO MAX Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 207 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.3.5 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Serial Communications Interface This device has one SCI peripheral. SCI is a two-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit baud-select register. Features of the SCI module include: ? Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin NOTE: Both pins can be used as GPIO if not used for SCI. – Baud rate programmable to 64K different rates ? Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits ? Four error-detection flags: parity, overrun, framing, and break detection ? Two wake-up multiprocessor modes: idle-line and address bit ? Half- or full-duplex operation ? Double-buffered receive and transmit functions ? Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) – Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions) ? Separate enable bits for transmitter and receiver interrupts (except BRKDT) ? NRZ format NOTE All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no effect. ? Auto baud-detect hardware logic ? 16-level transmit and receive FIFO Figure 7-40 shows the Cf20;BACKGROUND-COLOR:#4ae2f7">28x SCI peripheral. 208 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 7-40. SCI (Cf20;BACKGROUND-COLOR:#4ae2f7">28x) Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 209 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.3.5.1 Architecture The major elements used in full-duplex operation include: ? A transmitter (TX) and its major registers: – SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be transmitted – TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts data onto the SCITXD pin, one bit at a time ? A receiver (RX) and its major registers: – RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, one bit at a time – SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data from a remote processor is loaded into the RXSHF register and then into the SCIRXBUF and SCIRXEMU registers ? A programmable baud generator ? Data-memory-mapped control and status registers enable the CPU to access the I2 C module registers and FIFOs. The SCI receiver and transmitter can operate either independently or simultaneously. 7.3.5.2 Multiprocessor and Asynchronous Communication Modes The SCI has two multiprocessor protocols: the idle-line multiprocessor mode and the address-bit multiprocessor mode. These protocols allow efficient data transfer between multiple processors. The SCI offers the UART communications mode for interfacing with many popular peripherals. The asynchronous mode requires two lines to interface with many standard devices such as terminals and printers that use RS-232-C formats. Data transmission characteristics include: ? One start bit ? One to eight data bits ? An even/odd parity bit or no parity bit ? One or two stop bits with a programmed frequency 210 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.3.6 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Serial Peripheral Interface This device has one Cf20;BACKGROUND-COLOR:#4ae2f7">28x SPI. The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications between the DSP controller and external peripherals or another controller. Typical applications include external I/O or peripheral expansion via devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. The port supports a 16-level, receive-and-transmit FIFO for reducing CPU servicing overhead. The SPI module features include: ? SPISOMI: SPI slave-output/master-input pin ? SPISIMO: SPI slave-input/master-output pin ? SPISTE: SPI slave transmit-enable pin ? SPICLK: SPI serial-clock pin NOTE: All four pins can be used as GPIO, if the SPI module is not used. ? Two operational modes: master and slave ? Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the maximum speed of the I/O buffers used on the SPI pins. ? Data word length: 1 to 16 data bits ? Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. ? Simultaneous receive-and-transmit operation (transmit function can be disabled in software) ? Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. ? Twelve SPI module control registers: Located in control register frame beginning at address 7040h. NOTE All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (bits 7?0), and the upper byte (bits 15?8) is read as zeros. Writing to the upper byte has no effect. ? 16-level transmit and receive FIFO ? Delayed transmit control Figure 7-41 shows the Cf20;BACKGROUND-COLOR:#4ae2f7">28x SPI peripheral. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 211 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 7-41. SPI (Cf20;BACKGROUND-COLOR:#4ae2f7">28x) 212 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.3.6.1 Functional Overview The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is transmitted and received a half-cycle before the SPICLK transition. As a result, both controllers send and receive data simultaneously. The application software determines whether the data is meaningful or dummy data. There are three possible methods for data transmission: ? Master sends data; slave sends dummy data ? Master sends data; slave sends data ? Master sends dummy data; slave sends data The master can initiate a data transfer at any time because it controls the SPICLK signal. The software, however, determines how the master detects when the slave is ready to broadcast data. 7.3.6.2 SPI Electrical Data and Timing This section contains both Master Mode and Slave Mode timing data. 7.3.6.2.1 Master Mode Timing Table 7-40 lists the master mode timing (clock phase = 0) and Table 7-41 lists the timing (clock phase = 1). Figure 7-42 and Figure 7-43 show the timing waveforms. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 213 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-40. SPI Master Mode External Timing (Clock Phase = 0)(1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD SPIBRR = 0 OR 2 AND SPIBRR > 3 NO. UNIT MIN MAX MIN MAX 1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 1f20;BACKGROUND-COLOR:#4ae2f7">28tc(LCO) 5tc(LCO) 127tc(LCO) ns 2 tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns (clock polarity = 0) tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) (clock polarity = 1) 3 tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) ns (clock polarity = 0) tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) (clock polarity = 1) 4 td(SPCH-SIMO)M Delay time, SPICLK high to SPISIMO 10 10 ns valid (clock polarity = 0) td(SPCL-SIMO)M Delay time, SPICLK low to SPISIMO 10 10 valid (clock polarity = 1) 5 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 ns SPICLK low (clock polarity = 0) tv(SPCH-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 SPICLK high (clock polarity = 1) 8 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK 35 35 ns low (clock polarity = 0) tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK 35 35 high (clock polarity = 1) 9 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 ns SPICLK low (clock polarity = 0) tv(SPCH-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 SPICLK high (clock polarity = 1) (1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1) (3) tc(LCO) = LSPCLK cycle time (4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX. (5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6). 214 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 7-42. SPI Master Mode External Timing (Clock Phase = 0) Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 215 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-41. SPI Master Mode External Timing (Clock Phase = 1)(1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD SPIBRR = 0 OR 2 AND SPIBRR > 3 NO. UNIT MIN MAX MIN MAX 1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 1f20;BACKGROUND-COLOR:#4ae2f7">28tc(LCO) 5tc(LCO) 127tc(LCO) ns 2 tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns (clock polarity = 0) tw(SPCL))M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) (clock polarity = 1) 3 tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) ns (clock polarity = 0) tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) (clock polarity = 1) 6 tsu(SIMO-SPCH)M Setup time, SPISIMO data valid before 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 ns SPICLK high (clock polarity = 0) tsu(SIMO-SPCL)M Setup time, SPISIMO data valid before 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 SPICLK low (clock polarity = 1) 7 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 ns SPICLK high (clock polarity = 0) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 SPICLK low (clock polarity = 1) 10 tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high 35 35 ns (clock polarity = 0) tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low 35 35 (clock polarity = 1) 11 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 ns SPICLK high (clock polarity = 0) tv(SPCL-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 SPICLK low (clock polarity = 1) (1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25-MHz MAX, master mode receive 12.5 MHz MAX Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5 MHz MAX. (4) tc(LCO) = LSPCLK cycle time (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). 216 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 7-43. SPI Master Mode External Timing (Clock Phase = 1) Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 217 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.3.6.2.2 SPI Slave Mode Timing Table 7-42 lists the slave mode external timing (clock phase = 0) and Table 7-43 (clock phase = 1). Figure 7-44 and Figure 7-45 show the timing waveforms. Table 7-42. SPI Slave Mode External Timing (Clock Phase = 0)(1) (2) (3) (4) (5) NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 4tc(LCO) ns 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S 14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S 15 td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 35 ns td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 35 16 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low 0.75tc(SPC)S ns (clock polarity = 0) tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high 0.75tc(SPC)S (clock polarity = 1) 19 tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 35 ns tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 35 20 tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low 0.5tc(SPC)S – 10 ns (clock polarity = 0) tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high 0.5tc(SPC)S – 10 (clock polarity = 1) (1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX. (4) tc(LCO) = LSPCLK cycle time (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). 218 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 7-44. SPI Slave Mode External Timing (Clock Phase = 0) Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 219 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-43. SPI Slave Mode External Timing (Clock Phase = 1)(1) (2) (3) (4) NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 8tc(LCO) ns 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S 14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S 17 tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S ns tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S 18 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low 0.75tc(SPC)S ns (clock polarity = 1) tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high 0.75tc(SPC)S (clock polarity = 0) 21 tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 35 ns tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 35 22 tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high 0.5tc(SPC)S – 10 ns (clock polarity = 0) tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low 0.5tc(SPC)S – 10 (clock polarity = 1) (1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX. (4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 7-45. SPI Slave Mode External Timing (Clock Phase = 1) 220 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.3.7 Cf20;BACKGROUND-COLOR:#4ae2f7">28x Multichannel Buffered Serial Port This device provides one high-speed McBSP that allows direct interface to codecs and other devices. The CPU accesses data, control, and status information. The MCBSP also supports ?DMA transfers. The McBSP consists of a data-flow path and a control path connected to external devices by six pins. Data is communicated to devices interfaced with the McBSP via the data transmit (DX) pin for transmission and via the data receive (DR) pin for reception. Control information in the form of clocking and frame synchronization is communicated via the following pins: CLKX (transmit clock), CLKR (receive clock), FSX (transmit frame synchronization), and FSR (receive frame synchronization). The CPU and the DMA controller communicate with the McBSP through 16-bit-wide registers accessible via the internal peripheral bus. The CPU or the DMA controller writes the data to be transmitted to the data transmit registers (DXR1, DXR2). Data written to the DXRs is shifted out to DX via the transmit shift registers (XSR1, XSR2). Similarly, receive data on the DR pin is shifted into the receive shift registers (RSR1, RSR2) and copied into the receive buffer registers (RBR1, RBR2). The contents of the RBRs is then copied to the DRRs, which can be read by the CPU or the DMA controller. This method allows simultaneous movement of internal and external data communications. DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted) if the serial word length is 8 bits, 12 bits, or 16 bits. For larger word lengths, these registers are needed to hold the most significant bits. The frame and clock loop-back is implemented at chip level to enable CLKX and FSX to drive CLKR and FSR. If the loop-back is enabled, the CLKR and FSR get their signals from the CLKX and FSX pads instead of the CLKR and FSR pins. Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 221 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn McBSP features include: ? Full-duplex communication ? Double-buffered transmission and triple-buffered reception, allowing a continuous data stream ? Independent clocking and framing for reception and transmission ? The capability to send interrupts to the CPU and to send DMA events to the DMA controller ? 1f20;BACKGROUND-COLOR:#4ae2f7">28 channels for transmission and reception ? Multichannel selection modes that enable or disable block transfers in each of the channels ? Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D and D/A devices ? Support for external generation of clock signals and frame-synchronization signals ? A programmable sample rate generator for internal generation and control of clock signals and frame synchronization signals ? Programmable polarity for frame-synchronization pulses and clock signals ? Direct interface to: – T1/E1 framers – IOM-2 compliant devices – AC97-compliant devices (the necessary multi-phase frame capability is provided) – I2S compliant devices – SPI devices ? A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits NOTE A value of the chosen data size is referred to as a serial word or word in this section. Elsewhere, word is used to describe a 16-bit value. ? ?-law and A-law companding ? The option of transmitting/receiving 8-bit data with the LSB first ? Status bits for flagging exception/error conditions ? ABIS mode is not supported Figure 7-46 shows the Cf20;BACKGROUND-COLOR:#4ae2f7">28x McBSP peripheral. 222 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Figure 7-46. McBSP (Cf20;BACKGROUND-COLOR:#4ae2f7">28x) Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 223 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 7.3.7.1 McBSP Electrical Data and Timing 7.3.7.1.1 McBSP Transmit and Receive Timing Table 7-44. McBSP Timing Requirements(1) (2) NO. MIN MAX UNIT McBSP module clock (CLKG, CLKX, CLKR) range 1 kHz 25 (3) MHz McBSP module cycle time (CLKG, CLKX, CLKR) range 40 ns 1 ms M11 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P ns M12 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 7 ns M13 tr(CKRX) Rise time, CLKR/X CLKR/X ext 7 ns M14 tf(CKRX) Fall time, CLKR/X CLKR/X ext 7 ns M15 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 18 ns CLKR ext 2 M16 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 0 ns CLKR ext 6 M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 18 ns CLKR ext 5 M18 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 0 ns CLKR ext 3 M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 18 ns CLKX ext 2 M20 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 0 ns CLKX ext 6 (1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed. (3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed limit (30 MHz). 224 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 7-45. McBSP Switching Characteristics(1) (2) over recommended operating conditions (unless otherwise noted) NO. PARAMETER MIN MAX UNIT M1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns M2 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D – 5 (3) D + 5 (3) ns M3 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C – 5 (3) C + 5 (3) ns M4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int 0 4 ns CLKR ext 3 27 M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int 0 4 ns CLKX ext 3 27 M6 tdis(CKXH-DXHZ) Disable time, CLKX high to DX high impedance CLKX int 8 ns following last data bit CLKX ext 14 M7 td(CKXH-DXV) Delay time, CLKX high to DX valid. CLKX int 9 ns This applies to all bits except the first bit transmitted. CLKX ext f20;BACKGROUND-COLOR:#4ae2f7">28 Delay time, CLKX high to DX valid DXENA = 0 CLKX int 8 CLKX ext 14 Only applies to first bit transmitted when DXENA = 1 CLKX int P + 8 in Data Delay 1 or 2 (XDATDLY=01b or CLKX ext P + 14 10b) modes M8 ten(CKXH-DX) Enable time, CLKX high to DX driven DXENA = 0 CLKX int 0 ns CLKX ext 6 Only applies to first bit transmitted when DXENA = 1 CLKX int P in Data Delay 1 or 2 (XDATDLY=01b or CLKX ext P + 6 10b) modes M9 td(FXH-DXV) Delay time, FSX high to DX valid DXENA = 0 FSX int 8 ns FSX ext 14 Only applies to first bit transmitted when DXENA = 1 FSX int P + 8 in Data Delay 0 (XDATDLY=00b) mode. FSX ext P + 14 M10 ten(FXH-DX) Enable time, FSX high to DX driven DXENA = 0 FSX int 0 ns FSX ext 6 Only applies to first bit transmitted when DXENA = 1 FSX int P in Data Delay 0 (XDATDLY=00b) mode FSX ext P + 6 (1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) 2P = 1/CLKG in ns. (3) C = CLKRX low pulse width = P D = CLKRX high pulse width = P Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 225 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Figure 7-47. McBSP Receive Timing Figure 7-48. McBSP Transmit Timing 226 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 7.3.7.1.2 McBSP as SPI Master or Slave Timing Table 7-46. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) MASTER SLAVE NO. UNIT MIN MAX MIN MAX M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 8P – 10 ns M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 8P – 10 ns M32 tsu(BFXL-CKXH) Setup time, FSX low before CLKX high 8P + 10 ns M33 tc(CKX) Cycle time, CLKX 2P(1) 16P ns (1) 2P = 1/CLKG Table 7-47. McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 0) MASTER SLAVE NO. PARAMETER UNIT MIN MAX MIN MAX M24 th(CKXL-FXL) Hold time, FSX low after CLKX low 2P(1) ns M25 td(FXL-CKXH) Delay time, FSX low to CLKX high P ns Mf20;BACKGROUND-COLOR:#4ae2f7">28 tdis(FXH-DXHZ) Disable time, DX high impedance following 6 6P + 6 ns last data bit from FSX high M29 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) 2P = 1/CLKG For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns. Figure 7-49. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 227 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-48. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) MASTER SLAVE NO. UNIT MIN MAX MIN MAX M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high 16P + 10 ns M42 tc(CKX) Cycle time, CLKX 2P(1) 16P ns (1) 2P = 1/CLKG Table 7-49. McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 0) MASTER SLAVE NO. PARAMETER UNIT MIN MAX MIN MAX M34 th(CKXL-FXL) Hold time, FSX low after CLKX low P ns M35 td(FXL-CKXH) Delay time, FSX low to CLKX high 2P(1) ns M37 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit P + 6 7P + 6 ns from CLKX low M38 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) 2P = 1/CLKG For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With a maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16; that is, 4.6875 MHz and P = 13.3 ns. Figure 7-50. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 2f20;BACKGROUND-COLOR:#4ae2f7">28 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 Table 7-50. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) MASTER SLAVE NO. UNIT MIN MAX MIN MAX M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 8P + 10 ns M52 tc(CKX) Cycle time, CLKX 2P(1) 16P ns (1) 2P = 1/CLKG Table 7-51. McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 1) MASTER SLAVE NO. PARAMETER UNIT MIN MAX MIN MAX M43 th(CKXH-FXL) Hold time, FSX low after CLKX high 2P(1) ns M44 td(FXL-CKXL) Delay time, FSX low to CLKX low P ns M47 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from 6 6P + 6 ns FSX high M48 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) 2P = 1/CLKG For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16; that is, 4.6875 MHz and P = 13.3 ns. Figure 7-51. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Copyright ? 2011–2014, Texas Instruments Incorporated Peripheral Information and Timings 229 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn Table 7-52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) MASTER SLAVE NO. UNIT MIN MAX MIN MAX M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 8P – 10 ns M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 8P – 10 ns M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 16P + 10 ns M61 tc(CKX) Cycle time, CLKX 2P(1) 16P ns (1) 2P = 1/CLKG Table 7-53. McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 1)(1) MASTER(2) SLAVE NO. PARAMETER UNIT MIN MAX MIN MAX M53 th(CKXH-FXL) Hold time, FSX low after CLKX high P ns M54 td(FXL-CKXL) Delay time, FSX low to CLKX low 2P(1) ns M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid –2 0 3P + 6 5P + 20 ns M56 tdis(CKXH-DXHZ) Disable time, DX high impedance following last P + 6 7P + 6 ns data bit from CLKX high M57 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) 2P = 1/CLKG (2) C = CLKX low pulse width = P D = CLKX high pulse width = P For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns. Figure 7-52. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 230 Peripheral Information and Timings Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 8 Device and Documentation Support 8.1 Device Support 8.1.1 Development Support TI offers an extensive line of development tools, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). The following products support development of processor applications: Software Development Tools: Code Composer Studio IDE: including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (SYS/BIOS), which provides the basic run-time target software needed to support any processor application. Hardware Development Tools: Extended Development System ( XDS?) Emulator For a complete listing of development-support tools for the processor platform, visit the Texas Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 8.1.2 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all Concerto MCU devices and support tools. Each Concerto MCU commercial family member has one of three prefixes: x, p, or no prefix (for example, xFf20;BACKGROUND-COLOR:#4ae2f7">28M35H52C1RFPT). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (with prefix x for devices and TMDX for tools) through fully qualified production devices/tools (with no prefix for devices and TMDS, instead of TMDX, for tools). xFf20;BACKGROUND-COLOR:#4ae2f7">28M35... Experimental device that is not necessarily representative of the final device's electrical specifications pFf20;BACKGROUND-COLOR:#4ae2f7">28M35... Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification Ff20;BACKGROUND-COLOR:#4ae2f7">28M35... Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development-support product Devices with prefix x or p and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices with prefix of x or p have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. Copyright ? 2011–2014, Texas Instruments Incorporated Device and Documentation Support 231 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, RFP) and temperature range (for example, T). For device part numbers and further ordering information of Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x devices in the RFP package type, see the TI website (www.ti.com) or contact your TI sales representative. For additional description of the device nomenclature markings on the die, see the Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Concerto MCU Silicon Errata (literature number SPRZ357). Figure 8-1. Device Nomenclature 8.2 Documentation Support The following documents describe the MCU. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box. SPRUH22 Concerto Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Technical Reference Manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the Ff20;BACKGROUND-COLOR:#4ae2f7">28M35x Microcontroller Processors. SPRZ357 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Concerto MCU Silicon Errata describes known advisories on silicon and provides workarounds. 232 Device and Documentation Support Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B www.ti.com.cn ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 8.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 8-1. Related Links TECHNICAL TOOLS & SUPPORT & PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Click here Click here Click here Click here Click here Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Click here Click here Click here Click here Click here Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Click here Click here Click here Click here Click here Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Click here Click here Click here Click here Click here Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Click here Click here Click here Click here Click here Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Click here Click here Click here Click here Click here 8.4 社社区区资资源源下列链接提供到 TI 社区资源的连接. 链接的内容由各个分销商"按照原样"提供. 这些内容并不构成 TI 技术规范和标准且不一定反映 TI 的观点;请见 TI 的使用条款. TI E2E 社社区区TI 工工程程师师间间(E2E) 社社区区此社区的创建目的是为了促进工程师之间协作. 在e2e.ti.com 中,您可以咨询问题、共享知识、探索思路,在研发工程师的帮助下解决问题. 德德州州仪仪器器(TI) 嵌嵌入入式式处处理理器器维维基基网网站站德德州州仪仪器器(TI) 嵌嵌入入式式处处理理器器维维基基网网站站. . 此网站的建立是为了帮助开发人员从德州仪器 (TI) 的嵌入式处理器入门并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长. 8.5 Trademarks Concerto, PowerPAD, TMS320C2000, Piccolo, Delfino, Code Composer Studio, Texas Instruments, XDS are trademarks of Texas Instruments. ARM, Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. Freescale is a trademark of Freescale Semiconductor, Inc. Philips is a registered trademark of Koninklijke Philips Electronics N.V. Corporation. Bosch is a registered trademark of Robert Bosch GmbH Corporation. All other trademarks are the property of their respective owners. 8.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions. Copyright ? 2011–2014, Texas Instruments Incorporated Device and Documentation Support 233 Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B, Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B ZHCS295H –JUNE 2011–REVISED FEBRUARY 2014 www.ti.com.cn 9 Mechanical Packaging and Orderable Information 9.1 Thermal Data for RFP Package Table 9-1 shows the thermal data. See Section 6.2 for more information on thermal design considerations. Table 9-1. Thermal Model 144-Pin RFP Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA [°C/W] High k PCB 18.8 11.5 10.0 8.6 ΨJT [°C/W] 0.3 0.2 0.3 0.3 ΨJB 4.8 4.6 4.5 4.4 θJC 6.3 θJB 4.4 9.2 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 234 Mechanical Packaging and Orderable Information Copyright ? 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B 重重要要声声明明德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改, 并有权根据 JESD48 最新标准中止提供任何产品和服务.客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的.所有产品的销售都遵循在订单确认时所提供的TI 销售条款与条件. TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范.仅在 TI 保证的范围内,且TI 认为有必要时才会使用测试或其它质量控制技术.除非适用法律做出了硬性规定,否则没有必要对每种组件的所有参数进行测试. TI 对应用帮助或客户产品设计不承担任何义务.客户应对其使用 TI 组件的产品和应用自行负责.为尽量减小与客户产品和应用相关的风险, 客户应提供充分的设计与操作安全措施. TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予的直接或隐含权限作出任何保证或解释.TI 所发布的与第三方产品或服务有关的信息,不能构成从 TI 获得使用这些产品或服务的许可、授权、或认可.使用此类信息可能需要获得第三方的专利权或其它知识产权方面的许可,或是 TI 的专利权或其它知识产权方面的许可. 对于 TI 的产品手册或数据表中 TI 信息的重要部分,仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况下才允许进行复制.TI 对此类篡改过的文件不承担任何责任或义务.复制第三方的信息可能需要服从额外的限制条件. 在转售 TI 组件或服务时,如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分,则会失去相关 TI 组件或服务的所有明示或暗示授权,且这是不正当的、欺诈性商业行为.TI 对任何此类虚假陈述均不承担任何责任或义务. 客户认可并同意,尽管任何应用相关信息或支持仍可能由 TI 提供,但他们将独力负责满足与其产品及在其应用中使用 TI 产品相关的所有法律、法规和安全相关要求.客户声明并同意,他们具备制定与实施安全措施所需的全部专业技术和知识,可预见故障的危险后果、监测故障及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施.客户将全额赔偿因在此类安全关键应用中使用任何 TI 组件而对TI 及其代理造成的任何损失. 在某些场合中,为了推进安全相关应用有可能对 TI 组件进行特别的促销.TI 的目标是利用此类组件帮助客户设计和创立其特有的可满足适用的功能安全性标准和要求的终端产品解决方案.尽管如此,此类组件仍然服从这些条款. TI 组件未获得用于 FDA Class III(或类似的生命攸关医疗设备)的授权许可,除非各方授权官员已经达成了专门管控此类使用的特别协议. 只有那些 TI 特别注明属于军用等级或"增强型塑料"的TI 组件才是设计或专门用于军事/航空应用或环境的.购买者认可并同意,对并非指定面向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用,其风险由客户单独承担,并且由客户独力负责满足与此类使用相关的所有法律和法规要求. TI 已明确指定符合 ISO/TS16949 要求的产品,这些产品主要用于汽车.在任何情况下,因使用非指定产品而无法达到 ISO/TS16949 要求,TI不承担任何责任. 产品应用数字音频 www.ti.com.cn/audio 通信与电信 www.ti.com.cn/telecom 放大器和线性器件 www.ti.com.cn/amplifiers 计算机及周边 www.ti.com.cn/computer 数据转换器 www.ti.com.cn/dataconverters 消费电子 www.ti.com/consumer-apps DLP? 产品 www.dlp.com 能源 www.ti.com/energy DSP - 数字信号处理器 www.ti.com.cn/dsp 工业应用 www.ti.com.cn/industrial 时钟和计时器 www.ti.com.cn/clockandtimers 医疗电子 www.ti.com.cn/medical 接口 www.ti.com.cn/interface 安防应用 www.ti.com.cn/security 逻辑 www.ti.com.cn/logic 汽车电子 www.ti.com.cn/automotive 电源管理 www.ti.com.cn/power 视频和影像 www.ti.com.cn/video 微控制器 (MCU) www.ti.com.cn/microcontrollers RFID 系统 www.ti.com.cn/rfidsys OMAP应用处理器 www.ti.com/omap 无线连通性 www.ti.com.cn/wirelessconnectivity 德州仪器在线技术支持社区 www.deyisupport.com IMPORTANT NOTICE 邮寄地址: 上海市浦东新区世纪大道1568 号,中建大厦32 楼邮政编码: 200122 Copyright ? 2014, 德州仪器半导体技术(上海)有限公司 PACKAGE OPTION ADDENDUM www.ti.com 22-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B1RFPQ PREVIEW HTQFP RFP 144 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B1RFPQ Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B1RFPS ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B1RFPS Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B1RFPT ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35E20B1RFPT Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C1RFPQ PREVIEW HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C1RFPQ Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C1RFPS ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C1RFPS Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C1RFPT ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H22C1RFPT Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C1RFPS ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C1RFPS Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C1RFPT ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C1RFPT Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B1RFPS ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B1RFPS Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B1RFPT ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M20B1RFPT Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C1RFPS ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C1RFPS Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C1RFPT ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C1RFPT Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C1RFPS ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C1RFPS Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M52C1RFPT ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 Ff20;BACKGROUND-COLOR:#4ae2f7">28M35M22C1RFPT XFf20;BACKGROUND-COLOR:#4ae2f7">28M35H52C1RFPT ACTIVE HTQFP RFP 144 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 X Ff20;BACKGROUND-COLOR:#4ae2f7">28M35H52C1RFPT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PACKAGE OPTION ADDENDUM www.ti.com 22-Jun-2014 Addendum-Page 2 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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