国立东华大学电机工程研究所 硕士论文
指导教授 : 翁若敏 博士
使用晶片上回路滤波器之 900MHz 2V 13.62mW 互补式金氧半锁相回路 A 2V 13.62mW 900MHz CMOS Phase-Locked Loop with On-Chip Loop Filter
研究生 : 贾颖钧
撰
中华民国九十二年七月
A 2V 13.62mW 900MHz CMOS Phase-Locked Loop with On-Chip Loop Filter
Student :
Ying-Chun Chia
Advisor : Dr. Ro-Min Weng
A Thesis Submitted to Institute of Electrical Engineering College of Sciences and Engineering National Dong-Hwa University In Partial Fulfillment of the Requirements for the Degree of Master in Electrical Engineering July 2003 Hualien, Taiwan, Republic of China
摘要
互补式金氧半锁相回路为广泛应用於电子与通讯电路中之重要 元件,它的用途为解决积体电路在高速及高整合度环境下的时脉误差 及频率合成的问题.为了要实现射频至基频系统单晶片,高效能的锁 相回路是必需的.所以,实现具高速,低相位杂讯(低抖动)与低功率 消耗效能之晶片上锁相回路是目前设计上的主要目标. 本论文设计了一操作於 900MHz 频段的锁相回路,使用的制程为 TSMC 0.35-m 1p4m 逻辑的 CMOS 制程,论文中的锁相回路包括了 两级压控环型振荡器,除频器,相位频率侦测器,电荷帮浦与晶片上 被动回路滤波器.为降低由电源供应端注入之杂讯,环型振荡器采用 差动式的架构; 并且为达到高频操作与功率消耗最小化,振荡器只使 用了两个延迟单元.在 900MHz 的载波频率,振荡器的相位杂讯为 -102dBc/Hz 在距载波 600KHz 之频率偏移处,功率消耗为 6.2mW. 此外,在除频器电路中,我们将介绍并分析一种导管式技术之单相位 边缘触发比例式的高速逻辑正反器和 D 型正反器,此技术非常适合 於高速同步计数器之设计.为了降低锁相回路的抖动,相位频率侦测 器为无死带设计.回路滤波器为二阶低通滤波器. 最后,电路在工作电压 2V 下,HSPICE 的布局前模拟结果显示 了锁相回路的 long-term jitter 为 35ps,全部的功率消耗为 13.62mW, 而回路的锁定时间为 1.85s.在布局后模拟结果方面: long-term jitter 为 280ps,功率消耗为 14.1mW,而回路的锁定时间为 3.26s.整个 锁相回路晶片面积(包含 PAD)为 1688 x 1656 m2 .
I
ABSTRACT
CMOS phase-locked loops (PLLs) are important components widely used in the electronic and communication circuits. They are used to solve the clock skew and frequency synthesis problems of ICs in a fast operation speed and highly integrated environment. In order to realize single-chip RF-to-baseband systems, high performance PLLs are required. Therefore, the main goal of current design is to implement on-chip PLLs with high-speed, low-phase noise (low-jitter)and low-power consumption performance. In this thesis, a 900MHz PLL is designed with the TSMC 0.35-m 1p4m logic silicide CMOS process. The PLL consists a two-stage voltage-controlled ring oscillator (ring VCO), a frequency divider, a phase frequency detector (PFD) with charge pump and an on-chip passive loop filter. The ring VCO has a differential structure to reduce the power-supply-injected noise. Only two delay cells are included in the oscillator to achieve high-frequency operation and minimize the power consumption. At 900MHz carrier frequency, the phase noise of the VCO is –102dBc/Hz at 600KHz frequency offset and the power consumption is 6.2mW. Besides, in the frequency divider a fast pipeline technique using single-phase edge-triggered ratioed high-speed logic flip-flops and D flip-flops is introduced and analyzed. The technique is suitable for realizing high-speed synchronous counters. The PFD design is for deadzone free to reduce the jitter of the PLL. The loop filter is a second- order low pass filter. Finally, with 2V supply voltage, the HSPICE pre-simulation results

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